diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-06-29 15:38:02 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-24 23:52:30 +0200 |
| commit | 9c4c6ab0c895a35d6bad33ecb2cb7f40eea98001 (patch) | |
| tree | 985930a055dc8ec3ac392e37cb90a525553590a8 /src/northbridge/intel/sandybridge | |
| parent | fe7b5d2fa6705a2b553244dda0452ca55c5730a2 (diff) | |
| download | coreboot-9c4c6ab0c895a35d6bad33ecb2cb7f40eea98001.tar.xz | |
ELOG: Fix boot count increment for non-wake case
The count was only incrementing for a wake from S5 and
it was not incrementing in the normal reboot case.
Change-Id: I73bc6db6bd02e6c4677f7e44a5c098c6dcb51747
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1328
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index c7afa115cb..ff20c44833 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -64,6 +64,14 @@ static void sandybridge_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); printk(BIOS_DEBUG, " done.\n"); + +#if CONFIG_ELOG_BOOT_COUNT + /* Increment Boot Counter except when resuming from S3 */ + if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && + ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) + return; + boot_count_increment(); +#endif } static void sandybridge_setup_graphics(void) |