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authorArthur Heymans <arthur@aheymans.xyz>2018-01-25 00:33:45 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-07-30 19:11:00 +0000
commitaade90e68d26a90fbea0dccdaae3493bdf31829a (patch)
tree5e31d203c4beecb94250a458e67cc7d639f0b250 /src/northbridge/intel/sandybridge
parent6cd2c2f6ff792d1a170cd090e3347cfe2e14ac15 (diff)
downloadcoreboot-aade90e68d26a90fbea0dccdaae3493bdf31829a.tar.xz
nb/intel/gm45: Use common code for SMM in TSEG
This makes i82801ix use the common smm southbridge code to set up smm relocation and smi handler setup. This is needed in this change for the the smm relocation code relies on some southbridge functions provided in the common code. Some of the old code is kept for the Q35 qemu target. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Thinkpad X200: boots and going to and resuming from S3 still works fine. Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23419 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
-rw-r--r--src/northbridge/intel/sandybridge/northbridge.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 8c2aaf34e7..aab3931710 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -472,6 +472,11 @@ u32 northbridge_get_tseg_base(void)
return northbridge_get_base_reg(dev, TSEG);
}
+u32 northbridge_get_tseg_size(void)
+{
+ return CONFIG_SMM_TSEG_SIZE;
+}
+
void northbridge_write_smram(u8 smram)
{
pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram);