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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-23 22:38:08 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-26 09:38:42 +0000 |
| commit | a6c8b4becbd12fe6043557ca1e398c1a7c691007 (patch) | |
| tree | 688e3890a402661caacd8f3e61e8df63aabc9cee /src/northbridge/intel/sandybridge | |
| parent | 2a0a02f98f742ff921ac3a9a8ccbf7fe47690509 (diff) | |
| download | coreboot-a6c8b4becbd12fe6043557ca1e398c1a7c691007.tar.xz | |
nb/intel/sandybridge: Rewrite get_FRQ
The code is just clamping the frequency index to a valid range. Do it
with a helper function. Also, add a CPUID check, as Sandy Bridge will
eventually use this code.
Change-Id: I4c7aa5f7615c6edb1ab62fb004abb126df9d284b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_ivy.c | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 6484139a94..6ff82dd011 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include <commonlib/clamp.h> #include <console/console.h> #include <console/usb.h> #include <delay.h> @@ -9,24 +10,25 @@ #include "raminit_common.h" #include "raminit_tables.h" +#define IVB_MIN_DCLK_133_MULT 3 +#define IVB_MAX_DCLK_133_MULT 10 +#define IVB_MIN_DCLK_100_MULT 7 +#define IVB_MAX_DCLK_100_MULT 12 + /* Frequency multiplier */ -static u32 get_FRQ(u32 tCK, u8 base_freq) +static u32 get_FRQ(const ramctr_timing *ctrl) { - const u32 FRQ = 256000 / (tCK * base_freq); + const u32 FRQ = 256000 / (ctrl->tCK * ctrl->base_freq); - if (base_freq == 100) { - if (FRQ > 12) - return 12; - if (FRQ < 7) - return 7; - } else { - if (FRQ > 10) - return 10; - if (FRQ < 3) - return 3; + if (IS_IVY_CPU(ctrl->cpu)) { + if (ctrl->base_freq == 100) + return clamp_u32(IVB_MIN_DCLK_100_MULT, FRQ, IVB_MAX_DCLK_100_MULT); + + if (ctrl->base_freq == 133) + return clamp_u32(IVB_MIN_DCLK_133_MULT, FRQ, IVB_MAX_DCLK_133_MULT); } - return FRQ; + die("Unsupported CPU or base frequency."); } /* Get REFI based on frequency index, tREFI = 7.8usec */ @@ -204,7 +206,7 @@ static void find_cas_tck(ramctr_timing *ctrl) } /* Frequency multiplier */ - ctrl->FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); + ctrl->FRQ = get_FRQ(ctrl); printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); |