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| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/northbridge/intel/sch/sch.h | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
| download | coreboot-bde6d309dfafe58732ec46314a2d4c08974b62d4.tar.xz | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel/sch/sch.h')
| -rw-r--r-- | src/northbridge/intel/sch/sch.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h index 3eb082585d..9ac79ea8d1 100644 --- a/src/northbridge/intel/sch/sch.h +++ b/src/northbridge/intel/sch/sch.h @@ -36,7 +36,7 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data); #define DEFAULT_GPE0BASE 0x5C0 #define DEFAULT_SMMCNTRLBASE 0x3F703F76 -#define DEFAULT_RCBABASE 0xfed1c000 +#define DEFAULT_RCBABASE ((u8 *)0xfed1c000) #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ |