diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-08-03 15:44:27 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-04 21:28:52 +0000 |
| commit | ecec9474d808f532822091c5a6069f57abc1c81d (patch) | |
| tree | a60107551596d2bdd35c135865a1671c10b143e5 /src/northbridge/intel/x4x/memmap.c | |
| parent | f4fa1e1d06b5c68b746274c39f23cc8b05801d90 (diff) | |
| download | coreboot-ecec9474d808f532822091c5a6069f57abc1c81d.tar.xz | |
nb/intel/x4x: Change signature of `decode_pciebar`
Rename it and make it return an int, like other northbridges do.
Change-Id: I8bbf28350976547c83e039731d316e0911197d54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/x4x/memmap.c')
| -rw-r--r-- | src/northbridge/intel/x4x/memmap.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index ee1ec5e2be..6d40fafc67 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -57,7 +57,7 @@ u32 decode_tseg_size(const u32 esmramc) } } -u8 decode_pciebar(u32 *const base, u32 *const len) +int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; *len = 0; |