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author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 13:34:24 +0200 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-03 10:18:56 +0000 |
commit | 4c65bfc3e88fe6f4d6441fb7e51f78ed22dea709 (patch) | |
tree | 4e2a75d7f1c967e57bf20f7a2854695c69d37cec /src/northbridge/intel/x4x/northbridge.c | |
parent | cf3076eff17dc9c152fca6ec9012e7734ff88b4c (diff) | |
download | coreboot-4c65bfc3e88fe6f4d6441fb7e51f78ed22dea709.tar.xz |
nb/intel/x4x: Use common code for SMM in TSEG
This also caches the TSEG region and therefore increases MTRR usage
a little in some cases.
Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.
Tested on Intel DG41WV, resume from S3 still works fine.
Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25597
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x/northbridge.c')
-rw-r--r-- | src/northbridge/intel/x4x/northbridge.c | 51 |
1 files changed, 35 insertions, 16 deletions
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index bc7a5b39ae..d6094ac3da 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -29,14 +29,15 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> +#include <cpu/intel/smm/gen1/smi.h> static const int legacy_hole_base_k = 0xa0000 / 1024; static void mch_domain_read_resources(struct device *dev) { - u8 index, reg8; + u8 index; u64 tom, touud; - u32 tomk, tseg_sizek = 0, tolud, delta_cbmem; + u32 tomk, tolud, delta_cbmem; u32 pcie_config_base, pcie_config_size; u32 uma_sizek = 0; @@ -82,20 +83,8 @@ static void mch_domain_read_resources(struct device *dev) uma_sizek += gsm_sizek; printk(BIOS_DEBUG, "TSEG decoded, subtracting "); - reg8 = pci_read_config8(mch, D0F0_ESMRAMC); - reg8 >>= 1; - reg8 &= 3; - switch (reg8) { - case 0: - tseg_sizek = 1024; - break; /* TSEG = 1M */ - case 1: - tseg_sizek = 2048; - break; /* TSEG = 2M */ - case 2: - tseg_sizek = 8192; - break; /* TSEG = 8M */ - } + const u32 tseg_sizek = decode_tseg_size( + pci_read_config8(dev, D0F0_ESMRAMC)) >> 10; uma_sizek += tseg_sizek; tomk -= tseg_sizek; @@ -184,6 +173,36 @@ static const char *northbridge_acpi_name(const struct device *dev) return NULL; } +void northbridge_write_smram(u8 smram) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + + if (dev == NULL) + die("could not find pci 00:00.0!\n"); + + pci_write_config8(dev, D0F0_SMRAM, smram); +} + +/* + * Really doesn't belong here but will go away with parallel mp init, + * so let it be here for a while... + */ +int cpu_get_apic_id_map(int *apic_id_map) +{ + unsigned int i; + + /* Logical processors (threads) per core */ + const struct cpuid_result cpuid1 = cpuid(1); + /* Read number of cores. */ + const char cores = (cpuid1.ebx >> 16) & 0xf; + + /* TODO in parallel MP cpuid(1).ebx */ + for (i = 0; i < cores; i++) + apic_id_map[i] = i; + + return cores; +} + static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, |