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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-23 16:32:27 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:10:49 +0000 |
| commit | 2d7173d462c66cbbca6a5354c1ac719941e117d9 (patch) | |
| tree | 432c8fd4e65f30668e8e4f98d90a092a2a6fccd8 /src/northbridge/intel/x4x/raminit.c | |
| parent | fdbdca2ec3a3a28142791cd331fcf42da59e9d38 (diff) | |
| download | coreboot-2d7173d462c66cbbca6a5354c1ac719941e117d9.tar.xz | |
src: Remove unused 'include <cpu/x86/cache.h>'
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x/raminit.c')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index f1dc8817e6..797bc5a378 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -17,7 +17,6 @@ #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <arch/cpu.h> #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) |