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author | Arthur Heymans <arthur@aheymans.xyz> | 2017-05-09 18:38:14 +0200 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2017-05-22 09:06:36 +0200 |
commit | 27f0ca18bc6a9a65dcd59664330fdafbf7776847 (patch) | |
tree | 6d5a53b4f352460e43d440c0b9be95ee7c8f376c /src/northbridge/intel/x4x/x4x.h | |
parent | 93eac6a89d6aa4367436610a690c5aa0f040fc3a (diff) | |
download | coreboot-27f0ca18bc6a9a65dcd59664330fdafbf7776847.tar.xz |
nb/intel/x4x: Use a struct for dll settings instead of an array
This makes the code more readable since it avoids messing with two
dimensional arrays and needing remember what the indices mean.
Also introduces an unused coarse element which is 0 for all default
DLL settings on DDR2.
Change-Id: I28377d2d15d0e6a0d12545b837d6369e0dc26b92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
-rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 32d4b968e9..7d8f5cc442 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -240,6 +240,15 @@ enum chip_cap { /* as in DDR3 spd */ CHIP_CAP_16G = 6, }; +struct dll_setting { + u8 tap; + u8 pi; + u8 db_en; + u8 db_sel; + u8 clk_delay; + u8 coarse; +}; + struct timings { unsigned int CAS; enum fsb_clock fsb_clk; |