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author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-02 19:22:00 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2016-09-12 20:08:19 +0200 |
commit | 6e8b3c11105682e58ccb0574148654adecc532f7 (patch) | |
tree | bcd395a865e9d3f981e5ef9e99ff7b8bbfea3fe5 /src/northbridge/intel/x4x/x4x.h | |
parent | 6b72787d270077969869e9b17b88a63539f172b4 (diff) | |
download | coreboot-6e8b3c11105682e58ccb0574148654adecc532f7.tar.xz |
src/northbridge: Improve code formatting
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16414
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
-rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index ffad0d4735..aa5db7da5b 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -289,29 +289,29 @@ struct sysinfo { }; enum ddr2_signals { - CLKSET0 = 0, - CTRL0, - CLKSET1, - CMD, - CTRL1, - CTRL2, - CTRL3, - DQS1, - DQS2, - DQS3, - DQS4, - DQS5, - DQS6, - DQS7, - DQS8, - DQ1, - DQ2, - DQ3, - DQ4, - DQ5, - DQ6, - DQ7, - DQ8 + CLKSET0 = 0, + CTRL0, + CLKSET1, + CMD, + CTRL1, + CTRL2, + CTRL3, + DQS1, + DQS2, + DQS3, + DQS4, + DQS5, + DQS6, + DQS7, + DQS8, + DQ1, + DQ2, + DQ3, + DQ4, + DQ5, + DQ6, + DQ7, + DQ8 }; #ifndef __BOOTBLOCK__ |