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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-11 21:14:39 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-15 16:41:52 +0000 |
commit | bf53acca5e9c6b61086e42eb9e73fd4bb59a6f31 (patch) | |
tree | 8c2319996bb91648bc9db77f6a9dc428164f6225 /src/northbridge/intel/x4x/x4x.h | |
parent | dc7b2de88bb56d3284c3ab6227cffefd8c76836b (diff) | |
download | coreboot-bf53acca5e9c6b61086e42eb9e73fd4bb59a6f31.tar.xz |
nb/intel/x4x: Move boilerplate romstage to a common location
This adds 3 mb romstage callbacks:
- void mb_lpc_setup(void) to be used to set up the superio
- void mb_get_spd_map(u8 spd_map[4]) to get I2C addresses of SPDs
- (optional)mb_pre_raminit_setup(int s3_resume) to set up mainboard
specific things before the raminit.
Change-Id: Ic3b838856b3076ed05eeeea7c0656c2078462272
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36758
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
-rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 76e82d9494..e4a6c215d8 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -373,6 +373,9 @@ enum ddr2_signals { void x4x_early_init(void); void x4x_late_init(int s3resume); +void mb_lpc_setup(void); +void mb_get_spd_map(u8 spd_map[4]); +void mb_pre_raminit_setup(int s3_resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u32 decode_tseg_size(const u32 esmramc); |