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author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-06-15 11:03:00 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 08:54:13 +0000 |
commit | e951e8ec7f8a5a9d7b9b681526c3b16b67be15d4 (patch) | |
tree | 03e48a8ab3e58202dc393bad7435e88798bec805 /src/northbridge/intel/x4x/x4x.h | |
parent | 5778f772b59d50f2ac8d730893c5bdc3581d951b (diff) | |
download | coreboot-e951e8ec7f8a5a9d7b9b681526c3b16b67be15d4.tar.xz |
nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps}
Change-Id: I0442cc5bc54efd7e2c4e5496182c8df85acbcf91
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
-rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index a7efb172c5..57723364ab 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -378,8 +378,8 @@ u8 decode_pciebar(u32 *const base, u32 *const len); void sdram_initialize(int boot_path, const u8 *spd_map); void do_raminit(struct sysinfo *, int fast_boot); void rcven(struct sysinfo *s); -u32 fsb2mhz(u32 speed); -u32 ddr2mhz(u32 speed); +u32 fsb_to_mhz(u32 speed); +u32 ddr_to_mhz(u32 speed); u32 test_address(int channel, int rank); void dqsset(u8 ch, u8 lane, const struct dll_setting *setting); void dqset(u8 ch, u8 lane, const struct dll_setting *setting); |