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author | Arthur Heymans <arthur@aheymans.xyz> | 2016-12-30 21:07:18 +0100 |
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committer | Nico Huber <nico.h@gmx.de> | 2017-02-17 23:44:36 +0100 |
commit | ef7e98a2ac3449bc6a8d0cc73d7b54d41bc8bfa8 (patch) | |
tree | b4cd512e42e895f6ad1a2173f127af9d2df479cd /src/northbridge/intel/x4x/x4x.h | |
parent | 97e13d84c30c308c3b2bc629b38e6bcc9565dc3a (diff) | |
download | coreboot-ef7e98a2ac3449bc6a8d0cc73d7b54d41bc8bfa8.tar.xz |
nb/intel/x4x: Implement resume from S3 suspend
It rewrites the results of receive enable stored in the upper nvram
region, to avoid running receive enable again.
Some debug info is also printed about the self-refresh registers.
(Not enforcing a reset here, since 0 does not necessarily mean it's
not in self-refresh).
Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17998
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
-rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 66d765ab83..faae77595f 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -322,7 +322,7 @@ enum ddr2_signals { #ifndef __BOOTBLOCK__ void x4x_early_init(void); -void x4x_late_init(void); +void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len); |