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author | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-07 20:48:14 +0100 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2017-08-20 13:36:03 +0000 |
commit | 6d7a8c1125d17781fe2354eb316df247c82df741 (patch) | |
tree | 4b3522a81a6cc4ad9f11319301023aab80aa282e /src/northbridge/intel/x4x/x4x.h | |
parent | e464ccd116fe51137d9068c5db2edd7275ae8c9d (diff) | |
download | coreboot-6d7a8c1125d17781fe2354eb316df247c82df741.tar.xz |
nb/intel/x4x/raminit: Rework receive enable calibration
Moves receive enable calibration to a separate file to lighten
raminit.c a bit.
Receive enable calibration is quite similar to gm45 so it reuses some
of its function names.
The functional changes are:
* the minimum coarse is now reset for each channel;
* on the second fine search for DQS high, TAP overflow is handled by
increasing medium;
* start coarse at CAS + 1 instead of CAS - 1. Other Intel northbridges
do the same and the results are more in line with register dumps
from vendor bios.
These might improve stability.
TESTED on ga-g41m-es2l
Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
-rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 7d8f5cc442..9db6c12122 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -345,6 +345,7 @@ u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len); void sdram_initialize(int boot_path, const u8 *spd_map); void raminit_ddr2(struct sysinfo *); +void rcven(const struct sysinfo *); struct acpi_rsdp; #ifndef __SIMPLE_DEVICE__ |