summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/x4x
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-09 11:41:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-15 05:32:44 +0000
commit544878b56349a74e8cb7a0e9af899b5f7fc246fc (patch)
tree0a586dcbe6e70c94be6b7d123f43dd7c294dad68 /src/northbridge/intel/x4x
parent5bc641afebda5fd274ba713add4145651d9bc71d (diff)
downloadcoreboot-544878b56349a74e8cb7a0e9af899b5f7fc246fc.tar.xz
arch/x86: Add postcar_frame_common_mtrrs()
As most platforms will share the subset of enabling both low RAM WB and high ROM WP MTRRs, provide them with a single function. Add possibility for the platform to skip these if required. Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x')
-rw-r--r--src/northbridge/intel/x4x/memmap.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 254ca880fa..a61d64e61d 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -149,13 +149,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/