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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-03 21:28:40 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-07 05:42:15 +0000 |
commit | fe481eb3e5e8e8d39d892bfcfe085bc7d49ff886 (patch) | |
tree | b0e0c39376de50d41f3d6e21ed4b3aa47262d897 /src/northbridge/intel/x4x | |
parent | e119d86ca87937d45e67d00da722c28ac7ceaa9e (diff) | |
download | coreboot-fe481eb3e5e8e8d39d892bfcfe085bc7d49ff886.tar.xz |
northbridge/intel: Rename ram_calc.c to memmap.c
Use a name consistent with the more recent soc/intel.
Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/x4x')
-rw-r--r-- | src/northbridge/intel/x4x/Makefile.inc | 6 | ||||
-rw-r--r-- | src/northbridge/intel/x4x/memmap.c (renamed from src/northbridge/intel/x4x/ram_calc.c) | 0 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 3118b0980e..b7fd2fe7ae 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -19,16 +19,16 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y) romstage-y += early_init.c romstage-y += raminit.c romstage-y += raminit_ddr23.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += rcven.c romstage-y += raminit_tables.c romstage-y += dq_dqs.c ramstage-y += acpi.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += gma.c ramstage-y += northbridge.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/memmap.c index dda838760d..dda838760d 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/memmap.c |