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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-09 09:37:49 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-15 05:31:29 +0000
commit5bc641afebda5fd274ba713add4145651d9bc71d (patch)
tree849f5712a83c5eb895ae3aee24a26509c8a8421b /src/northbridge/intel/x4x
parentb3267e002e798e90ca09b11e42ea8949dccde2e7 (diff)
downloadcoreboot-5bc641afebda5fd274ba713add4145651d9bc71d.tar.xz
cpu/intel: Refactor platform_enter_postcar()
There are benefits in placing the postcar_frame structure in .bss and returning control to romstage_main(). Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/x4x')
-rw-r--r--src/northbridge/intel/x4x/memmap.c20
1 files changed, 5 insertions, 15 deletions
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index dda838760d..254ca880fa 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -145,33 +145,23 @@ void stage_cache_external_region(void **base, size_t *size)
+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
}
-/* platform_enter_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use,
- * and continues execution in postcar stage. */
-void platform_enter_postcar(void)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/
top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
- postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
+ postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
-
- run_postcar_phase(&pcf);
-
- /* We do not return here. */
}