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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-05 16:29:41 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-07 15:52:01 +0000 |
| commit | 1bc7b6e1350c4ba8eee10a859d10150b15b7b7e9 (patch) | |
| tree | 1751b8ebc3e6b6657d41d1b92e3e070fa8c8bb3e /src/northbridge/intel/x4x | |
| parent | ba092a9ab6e87fec458d6557d0114147e2713686 (diff) | |
| download | coreboot-1bc7b6e1350c4ba8eee10a859d10150b15b7b7e9.tar.xz | |
{gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function
Use already defined system_reset() and full_reset() functions.
Change-Id: Ic29fab70cf7f23d49c3eeeb97c984c523f973972
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 4d5bdce9ac..60d3b55531 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -22,7 +22,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <arch/cpu.h> -#include <halt.h> #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ #else @@ -624,9 +623,7 @@ static void checkreset_ddr2(int boot_path) reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); - printk(BIOS_DEBUG, "Reset...\n"); - outb(0xe, 0xcf9); - asm ("hlt"); + full_reset(); } pmcon2 |= 0x80; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); |