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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-05-26 15:08:06 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:37:50 +0000 |
| commit | 7345a17a43060e83a6761e86bc0f3314d9090e9c (patch) | |
| tree | a0d1c1ac4e10538fa5cb662403f9afe99a7b6017 /src/northbridge/intel/x4x | |
| parent | 5a9dbde59c5ef1c8aa1a0a96e8eeedd108c5ae5d (diff) | |
| download | coreboot-7345a17a43060e83a6761e86bc0f3314d9090e9c.tar.xz | |
nb/intel/x4x: Fix a few things in set_enhanced_mode
Some things were coding errors, other things need to be fsb specific.
Most things here don't seem to matter all that much but better to get
it right.
Change-Id: I1afa637a16a083c3a945ba3e2a71292b005736fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit_ddr23.c | 54 |
1 files changed, 44 insertions, 10 deletions
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 8242d6e4de..6cc5e32f59 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1815,6 +1815,7 @@ static void configure_mmap(struct sysinfo *s) static void set_enhanced_mode(struct sysinfo *s) { u8 ch, reg8; + u32 reg32; MCHBAR32(0xfb0) = 0x1000d024; MCHBAR32(0xfb4) = 0xc842; @@ -1825,7 +1826,7 @@ static void set_enhanced_mode(struct sysinfo *s) if (s->selected_timings.mem_clk <= MEM_CLOCK_800MHz) MCHBAR8(0x12f) = MCHBAR8(0x12f) | 0x2; else - MCHBAR8(0x12f) = MCHBAR8(0x12f) & 0x2; + MCHBAR8(0x12f) = MCHBAR8(0x12f) & ~0x2; MCHBAR8(0x6c0) = (MCHBAR8(0x6c0) & ~0xf0) | 0xa0; MCHBAR32(0xfa8) = 0x30d400; @@ -1843,15 +1844,48 @@ static void set_enhanced_mode(struct sysinfo *s) reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | 1); - MCHBAR32(0xfa0) = (MCHBAR32(0xfa0) & ~0x20002) | 0x2; - MCHBAR32(0xfa4) = (MCHBAR32(0xfa4) & ~0x219100c3) | 0x219100c2; - MCHBAR32(0x2c) = 0x44a53; + MCHBAR32(0xfa0) = (MCHBAR32(0xfa0) & ~0x20002) | 0x2 + | (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz + ? 0x20000 : 0); + reg32 = 0x219100c2; + if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) { + reg32 |= 1; + if (s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) + reg32 &= ~0x10000; + } else if (s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) { + reg32 &= ~0x10000; + } + MCHBAR32(0xfa4) = (MCHBAR32(0xfa4) & ~0x219100c3) | reg32; + reg32 = 0x44a00; + switch (s->selected_timings.fsb_clk) { + case FSB_CLOCK_1333MHz: + reg32 |= 0x62; + break; + case FSB_CLOCK_1066MHz: + reg32 |= 0x5a; + break; + default: + case FSB_CLOCK_800MHz: + reg32 |= 0x53; + break; + } + + MCHBAR32(0x2c) = reg32; MCHBAR32(0x30) = 0x1f5a86; MCHBAR32(0x34) = 0x1902810; MCHBAR32(0x38) = 0xf7000000; - MCHBAR32(0x3c) = 0x23014410; - MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0x8f038000) | 0x8f038000; - MCHBAR32(0x20) = 0x33001; + reg32 = 0x23014410; + if (s->selected_timings.fsb_clk > FSB_CLOCK_800MHz) + reg32 = (reg32 & ~0x2000000) | 0x44000000; + MCHBAR32(0x3c) = reg32; + reg32 = 0x8f038000; + if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) + reg32 &= ~0x4000000; + MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0x8f038000) | reg32; + reg32 = 0x00013001; + if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz) + reg32 |= 0x20000; + MCHBAR32(0x20) = reg32; pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~1); } @@ -1920,7 +1954,7 @@ static void power_settings(struct sysinfo *s) MCHBAR32(0x14) = 0x0010691f; MCHBAR32(0x18) = 0xdf6437f7; MCHBAR32(0x1c) = 0x0; - MCHBAR32(0x24) = (MCHBAR32(0x24) & ~0xe0000000) | 0x30000000; + MCHBAR32(0x24) = (MCHBAR32(0x24) & ~0xe0000000) | 0x60000000; MCHBAR32(0x44) = (MCHBAR32(0x44) & ~0x1fef0000) | 0x6b0000; MCHBAR16(0x115) = (u16) reg1; MCHBAR32(0x117) = (MCHBAR32(0x117) & ~0xffffff) | reg2; @@ -1943,8 +1977,8 @@ static void power_settings(struct sysinfo *s) MCHBAR32(0x300) = 0xc0b0a08; MCHBAR32(0x304) = 0x6040201; MCHBAR32(0x30c) = (MCHBAR32(0x30c) & ~0x43c0f) | 0x41405; - MCHBAR16(0x610) = 0x232; - MCHBAR16(0x612) = 0x2864; + MCHBAR16(0x610) = reg3; + MCHBAR16(0x612) = reg4; MCHBAR32(0x62c) = (MCHBAR32(0x62c) & ~0xc000000) | 0x4000000; MCHBAR32(0xae4) = 0; MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0xf0000) | 0x10000; |