diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-12-24 08:11:13 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-29 07:45:30 +0000 |
| commit | a8a9f34e9b7be8781c06c9d6fcc39f52bf31bd23 (patch) | |
| tree | b674190e4efe1c2a814a2638b3a20d92701c353d /src/northbridge/intel/x4x | |
| parent | e798e6a0b946fe5a3964bc38fb7783a219adf177 (diff) | |
| download | coreboot-a8a9f34e9b7be8781c06c9d6fcc39f52bf31bd23.tar.xz | |
sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables
Both southbridges need to be done at once since this southbridge code
is used for different northbridges, which fails to compile when done
separately.
This needs an acpi_name functions in the northbridge code to be
defined.
TESTED on Intel DG43GT: show correct PIRQ ACPI entries in
/sys/firmware/acpi/tables/SSDT.
Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/acpi/hostbridge.asl | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/northbridge.c | 17 |
2 files changed, 17 insertions, 3 deletions
diff --git a/src/northbridge/intel/x4x/acpi/hostbridge.asl b/src/northbridge/intel/x4x/acpi/hostbridge.asl index 530fdfafd9..90f15c78c1 100644 --- a/src/northbridge/intel/x4x/acpi/hostbridge.asl +++ b/src/northbridge/intel/x4x/acpi/hostbridge.asl @@ -229,6 +229,3 @@ Method (_CRS, 0, Serialized) Return (MCRS) } - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/x4x_pci_irqs.asl" diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 3e5022962a..0fcc297639 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -156,6 +156,22 @@ static void mch_domain_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32); } +static const char *northbridge_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) + return NULL; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0, 0): + return "MCHC"; + } + + return NULL; +} + static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, @@ -163,6 +179,7 @@ static struct device_operations pci_domain_ops = { .scan_bus = pci_domain_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_name = northbridge_acpi_name, }; |