diff options
| author | Shelley Chen <shchen@google.com> | 2020-07-23 16:10:52 -0700 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2020-08-24 23:30:50 +0000 |
| commit | ad9cd687b83061391d44bfc55a625b5571ff32a9 (patch) | |
| tree | 4187e82feda28c383ab629c965a74f71cf336c61 /src/northbridge/intel/x4x | |
| parent | 73f8986ad27b528f94e8385cacdbec1a10373148 (diff) | |
| download | coreboot-ad9cd687b83061391d44bfc55a625b5571ff32a9.tar.xz | |
mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms
Create two new functions to fetch mrc_cache data (replacing
mrc_cache_get_current):
- mrc_cache_load_current: fetches the mrc_cache data and drops it into
the given buffer. This is useful for ARM platforms where the mmap
operation is very expensive.
- mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a
given buffer. This is useful for platforms where the mmap operation
is a no-op (like x86 platforms). As the name mentions, we are not
freeing the memory that we allocated with the mmap, so it is the
caller's responsibility to do so.
Additionally, we are replacing mrc_cache_latest with
mrc_cache_get_latest_slot_info, which does not check the validity of
the data when retrieving the current mrc_cache slot. This allows the
caller some flexibility in deciding where they want the mrc_cache data
stored (either in an mmaped region or at a given address).
BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
reboot from ec console. Make sure memory training happens.
reboot from ec console. Make sure that we don't do training again.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 9f361b694e..a62771d676 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -610,8 +610,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map) { struct sysinfo s, *ctrl_cached; u8 reg8; - int fast_boot, cbmem_was_inited, cache_not_found; - struct region_device rdev; + int fast_boot, cbmem_was_inited; + size_t mrc_size; timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); @@ -620,10 +620,11 @@ void sdram_initialize(int boot_path, const u8 *spd_map) memset(&s, 0, sizeof(struct sysinfo)); - cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA, - MRC_CACHE_VERSION, &rdev); + ctrl_cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + MRC_CACHE_VERSION, + &mrc_size); - if (cache_not_found || (region_device_sz(&rdev) < sizeof(s))) { + if (!ctrl_cached || mrc_size < sizeof(s)) { if (boot_path == BOOT_PATH_RESUME) { /* Failed S3 resume, reset to come up cleanly */ system_reset(); @@ -632,9 +633,6 @@ void sdram_initialize(int boot_path, const u8 *spd_map) and therefore requiring valid cached settings */ full_reset(); } - ctrl_cached = NULL; - } else { - ctrl_cached = rdev_mmap_full(&rdev); } /* verify MRC cache for fast boot */ |