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authorArthur Heymans <arthur@aheymans.xyz>2018-09-05 20:39:39 +0200
committerFelix Held <felix-coreboot@felixheld.de>2018-09-16 18:57:20 +0000
commitb0c6cffb093d82b8a24b00e1914e5195bcc0b50d (patch)
tree7ff7d0c805cd41389399c58c3df008fd3d7f8fcf /src/northbridge/intel/x4x
parentf2c3d8076e6ed0d8f1e2bc83d61f1930ec9d1e18 (diff)
downloadcoreboot-b0c6cffb093d82b8a24b00e1914e5195bcc0b50d.tar.xz
nb/intel/x4x: Don't use cached settings if CPU FSB has been changed
Using the cached CPU FSB setting can simply be wrong, in which case it won't boot. Since the selected timings also depend on the CPU FSB, it is also best to not use cached timings at all when a change is detected. Tested on P5QC, swapped a 1333MHz FSB to a 800MHz FSB and it uses !fast_boot boot path. Change-Id: I12d91d0e892c15778409d7c00b27652ee52ca80c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/x4x')
-rw-r--r--src/northbridge/intel/x4x/raminit.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 9d37ada38f..4d34968678 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -669,9 +669,16 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
/* check SPD checksum to make sure the DIMMs haven't been
* replaced */
fast_boot = verify_spds(spd_map, ctrl_cached) == CB_SUCCESS;
- if (!fast_boot)
+ if (!fast_boot) {
printk(BIOS_DEBUG, "SPD checksums don't match,"
" dimm's have been replaced\n");
+ } else {
+ find_fsb_speed(&s);
+ fast_boot = s.max_fsb == ctrl_cached->max_fsb;
+ if (!fast_boot)
+ printk(BIOS_DEBUG,
+ "CPU FSB does not match and has been replaced\n");
+ }
} else {
fast_boot = boot_path == BOOT_PATH_RESUME;
}