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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-07 12:00:31 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-14 18:13:15 +0000 |
| commit | 1cfafe25e37d3a396a19bfe524af16284ff41070 (patch) | |
| tree | fa48bc17e9070649105b4ee48ffd7c20700e6332 /src/northbridge/intel/x4x | |
| parent | 7adc370dc79af1aacd6f811b9b28d01d595da702 (diff) | |
| download | coreboot-1cfafe25e37d3a396a19bfe524af16284ff41070.tar.xz | |
intel/{gm45,x4x},i82801{ix|jx}: Move enable_smbus() call
Change-Id: Idc7631abb550b31af722ccf3b69afdc01fdb616e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38268
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/romstage.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index eae87f3674..26d336bfd2 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -34,8 +34,6 @@ void mainboard_romstage_entry(void) u8 boot_path = 0; u8 s3_resume; - enable_smbus(); - #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) i82801jx_early_init(); #elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) |