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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-02-27 21:45:07 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-05-10 00:28:21 +0200 |
| commit | 293445ae1f93d38b86b1c1a3c9ee40ec96a36fac (patch) | |
| tree | 79015039e5506ce1c0db226f2ac7a4a30519fd37 /src/northbridge/intel/x4x | |
| parent | 6dcb789da9c04b9b4c9d4cff1a7602b72f97b1be (diff) | |
| download | coreboot-293445ae1f93d38b86b1c1a3c9ee40ec96a36fac.tar.xz | |
nb/intel/x4x: Add support for second PEG slot
Is only present on the P45 subtype of chipset.
Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/northbridge.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index c91e7c8b60..6ba45fee0b 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -196,8 +196,12 @@ static void x4x_init(void *const chip_info) struct device *const d0f0 = dev_find_slot(0, 0); /* Hide internal functions based on devicetree info. */ - for (dev = 3; dev > 0; --dev) { + for (dev = 6; dev > 0; --dev) { switch (dev) { + case 6: /* PEG1: only on P45 */ + fn = 0; + bit_base = 13; + break; case 3: /* ME */ fn = 3; bit_base = 6; @@ -206,10 +210,13 @@ static void x4x_init(void *const chip_info) fn = 1; bit_base = 3; break; - case 1: /* PEG */ + case 1: /* PEG0 */ fn = 0; bit_base = 1; break; + case 4: /* Nothing to do */ + case 5: + continue; } for (; fn >= 0; --fn) { const struct device *const d = |