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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 16:43:48 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:30:59 +0000 |
| commit | 45008930626bda902c8f37880e6f09d517b8cdd2 (patch) | |
| tree | be885c8deea5a176a9f0423b25a239df98ad7f8d /src/northbridge/intel/x4x | |
| parent | 3ab19b32a2d417a03e2b3d9942eae981dd951233 (diff) | |
| download | coreboot-45008930626bda902c8f37880e6f09d517b8cdd2.tar.xz | |
nb/intel/ironlake: Correct PCIEXBAR definition
This register resides within the SAD's config space, and is 64-bit.
Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/x4x')
0 files changed, 0 insertions, 0 deletions