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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-02-12 12:00:40 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-20 23:20:34 +0000 |
| commit | 7be74dbb38e41534055dbb27837e61f480c7db56 (patch) | |
| tree | 03e80d9b65f1fdc17463b55e4d6c5dfa140dde64 /src/northbridge/intel/x4x | |
| parent | cb304c1d85ff0a289c8a7244bf6e8adac07cd624 (diff) | |
| download | coreboot-7be74dbb38e41534055dbb27837e61f480c7db56.tar.xz | |
nb/x4x/raminit_ddr2: Refactor clock configuration slightly
The result is shorter and (IMHO) more readable code.
Change-Id: Ic51c05d7aa791250d775bd7a640213065d4caba0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge/intel/x4x')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit_ddr2.c | 31 |
1 files changed, 14 insertions, 17 deletions
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index e6ba2dcef8..022cbaa0b4 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -722,23 +722,20 @@ static void dll_ddr2(struct sysinfo *s) } FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { - clkset0(i, &dll_setting_667[CLKSET0]); - clkset1(i, &dll_setting_667[CLKSET1]); - ctrlset0(i, &dll_setting_667[CTRL0]); - ctrlset1(i, &dll_setting_667[CTRL1]); - ctrlset2(i, &dll_setting_667[CTRL2]); - ctrlset3(i, &dll_setting_667[CTRL3]); - cmdset(i, &dll_setting_667[CMD]); - } else { - clkset0(i, &dll_setting_800[CLKSET0]); - clkset1(i, &dll_setting_800[CLKSET1]); - ctrlset0(i, &dll_setting_800[CTRL0]); - ctrlset1(i, &dll_setting_800[CTRL1]); - ctrlset2(i, &dll_setting_800[CTRL2]); - ctrlset3(i, &dll_setting_800[CTRL3]); - cmdset(i, &dll_setting_800[CMD]); - } + const struct dll_setting *setting; + + if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) + setting = dll_setting_667; + else + setting = dll_setting_800; + + clkset0(i, &setting[CLKSET0]); + clkset1(i, &setting[CLKSET1]); + ctrlset0(i, &setting[CTRL0]); + ctrlset1(i, &setting[CTRL1]); + ctrlset2(i, &setting[CTRL2]); + ctrlset3(i, &setting[CTRL3]); + cmdset(i, &setting[CMD]); } // XXX if not async mode |