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authorYork Yang <york.yang@intel.com>2015-02-03 14:14:42 -0700
committerMartin Roth <gaumless@gmail.com>2015-02-06 00:58:50 +0100
commit114baa0a0ad8132964d8c60bd9583c339b6fcc51 (patch)
treebef9189699ebb201d9f1eff0010d30026a65001e /src/northbridge/intel
parent582b2aee0f5ac84339853551cca1f4d21e1e3fca (diff)
downloadcoreboot-114baa0a0ad8132964d8c60bd9583c339b6fcc51.tar.xz
intel/fsp_rangeley: Indent '#define' consistently
The indentations of #define are not consistent in chip.h. Update to make all #define indentations being aligned and put them after the variable declaration. Change-Id: I37550acac18bac3efddb580ef6b956be0e2b357a Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/8333 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel')
-rwxr-xr-x[-rw-r--r--]src/northbridge/intel/fsp_rangeley/chip.h25
1 files changed, 13 insertions, 12 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h
index d3828c7764..a8d0a1f137 100644..100755
--- a/src/northbridge/intel/fsp_rangeley/chip.h
+++ b/src/northbridge/intel/fsp_rangeley/chip.h
@@ -52,21 +52,22 @@ struct northbridge_intel_fsp_rangeley_config {
/* Enable the Rank Margin Tool, needs PrintDebugMessages */
uint8_t MrcRmtSupport;
-#define BIFURCATION_4_4_4_4 0
-#define BIFURCATION_4_4_8 1
-#define BIFURCATION_8_4_4 2
-#define BIFURCATION_8_8 3
-#define BIFURCATION_16 4
+ /* PCIe port bifurcation control */
uint8_t Bifurcation;
+ #define BIFURCATION_4_4_4_4 0
+ #define BIFURCATION_4_4_8 1
+ #define BIFURCATION_8_4_4 2
+ #define BIFURCATION_8_8 3
+ #define BIFURCATION_16 4
/* PCIe port de-emphasis control */
- #define DE_EMPHASIS_DEFAULT 0
- #define DE_EMPHASIS_MINUS_6_0_DB 1
- #define DE_EMPHASIS_MINUS_3_5_DB 2
- uint8_t PcdPcieRootPort1DeEmphasis;
- uint8_t PcdPcieRootPort2DeEmphasis;
- uint8_t PcdPcieRootPort3DeEmphasis;
- uint8_t PcdPcieRootPort4DeEmphasis;
+ uint8_t PcdPcieRootPort1DeEmphasis;
+ uint8_t PcdPcieRootPort2DeEmphasis;
+ uint8_t PcdPcieRootPort3DeEmphasis;
+ uint8_t PcdPcieRootPort4DeEmphasis;
+ #define DE_EMPHASIS_DEFAULT 0
+ #define DE_EMPHASIS_MINUS_6_0_DB 1
+ #define DE_EMPHASIS_MINUS_3_5_DB 2
};
#endif