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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-12-27 21:04:53 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-01-10 09:19:40 +0100
commit2fcf6f1cafca99105f2ce7485c81d8c9eb74e2de (patch)
tree9cda29c2afad79b60e16d49221ec3a3cea1f1f6d /src/northbridge/intel
parent1682b8d97a451b1ef96033a62f45b8196aa63715 (diff)
downloadcoreboot-2fcf6f1cafca99105f2ce7485c81d8c9eb74e2de.tar.xz
haswell: Fix MRC cache to use CBFS
Place the mrc.cache file at top of CBFS. There is no real requirement for it to have a fixed location though. Change-Id: Ibebe848a573b41788c9d84388be8ced68957f367 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7962 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/haswell/Kconfig10
-rw-r--r--src/northbridge/intel/haswell/Makefile.inc12
-rw-r--r--src/northbridge/intel/haswell/mrccache.c12
3 files changed, 17 insertions, 17 deletions
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index cac5c46431..0845a3f7b3 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -42,16 +42,6 @@ config CACHE_MRC_SIZE_KB
int
default 512
-# FIXME: build from rom size
-config MRC_CACHE_BASE
- hex
- default 0xff800000
-
-config MRC_CACHE_LOCATION
- hex
- depends on !CHROMEOS
- default 0x370000
-
config MRC_CACHE_SIZE
hex
depends on !CHROMEOS
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index f2577c7bd9..c8ebcdb99a 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -40,3 +40,15 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE))
mrc.bin-position := 0xfffa0000
mrc.bin-type := 0xab
+ifneq ($(CONFIG_CHROMEOS),y)
+$(obj)/mrc.cache: $(obj)/config.h
+ dd if=/dev/zero count=1 \
+ bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \
+ tr '\000' '\377' > $@
+
+cbfs-files-y += mrc.cache
+mrc.cache-file := $(obj)/mrc.cache
+mrc.cache-position := 0xfffe0000
+mrc.cache-type := 0xac
+endif
+
diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c
index a921e048dd..540bbf636a 100644
--- a/src/northbridge/intel/haswell/mrccache.c
+++ b/src/northbridge/intel/haswell/mrccache.c
@@ -66,16 +66,14 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache)
*/
static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
{
- u32 region_size;
#if CONFIG_CHROMEOS
- region_size = find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr);
+ return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr);
#else
- region_size = CONFIG_MRC_CACHE_SIZE;
- *mrc_region_ptr = (struct mrc_data_container *)
- (CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION);
-#endif
-
+ size_t region_size;
+ *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
+ "mrc.cache", 0xac, &region_size);
return region_size;
+#endif
}
/*