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authorElyes HAOUAS <ehaouas@noos.fr>2019-04-28 18:07:02 +0200
committerNico Huber <nico.h@gmx.de>2019-04-29 15:58:43 +0000
commit363b77177ea4bb7349dc418e355465b84d8accb5 (patch)
treef003fd2a1a812701e05d375c2fb8964473de0f9e /src/northbridge/intel
parentd45f33804db1e4181e2f657727adc51842aa9a60 (diff)
downloadcoreboot-363b77177ea4bb7349dc418e355465b84d8accb5.tar.xz
nb/intel/pineview: Use system_reset()
Use already defined system_reset() function. Change-Id: I32c731de0c30940d15fd01fec6f10b3b33c04370 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/pineview/romstage.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index 771434472e..bdb685b252 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -22,6 +22,7 @@
#include <console/console.h>
#include <device/pci_ops.h>
#include <cbmem.h>
+#include <cf9_reset.h>
#include <halt.h>
#include <romstage_handoff.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
@@ -113,8 +114,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (!cbmem_was_initted && s3resume) {
/* Failed S3 resume, reset to come up cleanly */
- outb(0x6, 0xcf9);
- halt();
+ system_reset();
}
romstage_handoff_init(s3resume);