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authorPatrick Rudolph <siro@das-labor.org>2016-04-20 18:00:27 +0200
committerNico Huber <nico.h@gmx.de>2016-04-29 13:11:35 +0200
commit588ccaa9a7d94da4f5a5b3579eb9e3d06c9f4a51 (patch)
tree6d3cfd20f25eb476d7fb047e4bd76f7a8e981df2 /src/northbridge/intel
parentfa6f861b574f27d5eb8df5e67dd8e2548779ecfc (diff)
downloadcoreboot-588ccaa9a7d94da4f5a5b3579eb9e3d06c9f4a51.tar.xz
nb/intel/sandybridge/raminit: fix regression "always use mrccache"
Fix regression introduced by: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Don't run channel_test on S3 resume as it overrides memory that might be in use. Fixes MCE events reported by the GNU/Linux kernel that low memory has been modified. Reset on failed s3 resume. Change-Id: Ibadea286619c7906225f86a93aaa0b4caf26cabe Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c21
1 files changed, 14 insertions, 7 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 042898dfb6..3c606e17c2 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -4038,7 +4038,7 @@ static void restore_timings(ramctr_timing * ctrl)
}
static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,
- int me_uma_size)
+ int s3_resume, int me_uma_size)
{
int err;
@@ -4148,9 +4148,11 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,
write_controller_mr(ctrl);
- err = channel_test(ctrl);
- if (err)
- return err;
+ if (!s3_resume) {
+ err = channel_test(ctrl);
+ if (err)
+ return err;
+ }
return 0;
}
@@ -4228,9 +4230,14 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck,
printk(BIOS_DEBUG, "Trying stored timings.\n");
memcpy(&ctrl, ctrl_cached, sizeof(ctrl));
- err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size);
+ err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size);
if (err) {
- /* no need to erase bad mrc cache here, it gets overritten on
+ if (s3resume) {
+ /* Failed S3 resume, reset to come up cleanly */
+ outb(0x6, 0xcf9);
+ halt();
+ }
+ /* no need to erase bad mrc cache here, it gets overwritten on
* successful boot. */
printk(BIOS_ERR, "Stored timings are invalid !\n");
fast_boot = 0;
@@ -4243,7 +4250,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck,
/* Get DDR3 SPD data */
dram_find_spds_ddr3(spds, &ctrl);
- err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size);
+ err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size);
}
if (err)
die("raminit failed");