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authorElyes HAOUAS <ehaouas@noos.fr>2020-04-29 09:09:12 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-26 15:11:33 +0000
commit5ac723e5a4a22bc9a08098cd59de5026b18d362d (patch)
tree1dd12f2f9c99d90dddfb08da50d7cf46264fc716 /src/northbridge/intel
parentb30fe36734df3c48ec35438052ee8b28bf7a6a44 (diff)
downloadcoreboot-5ac723e5a4a22bc9a08098cd59de5026b18d362d.tar.xz
nb/intel: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/gm45/iommu.c7
-rw-r--r--src/northbridge/intel/gm45/northbridge.c6
-rw-r--r--src/northbridge/intel/pineview/northbridge.c6
-rw-r--r--src/northbridge/intel/x4x/northbridge.c6
4 files changed, 6 insertions, 19 deletions
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 0d106b8e27..10e0d02066 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -36,17 +36,16 @@ void init_iommu()
const pci_devfn_t igd = PCI_DEV(0, 2, 0);
/* setup somewhere */
- u8 cmd = pci_read_config8(igd, PCI_COMMAND);
- cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_write_config8(igd, PCI_COMMAND, cmd);
+ pci_or_config16(igd, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0);
/* clear GTT, 2MB is enough (and should be safe) */
memset(bar, 0, 2<<20);
/* and now disable again */
+ u16 cmd = pci_read_config8(igd, PCI_COMMAND);
cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- pci_write_config8(igd, PCI_COMMAND, cmd);
+ pci_write_config16(igd, PCI_COMMAND, cmd);
pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0);
}
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index cd64dfe3dd..b3dbe16b75 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -178,14 +178,10 @@ static void mch_domain_set_resources(struct device *dev)
static void mch_domain_init(struct device *dev)
{
- u32 reg32;
-
struct device *mch = pcidev_on_root(0, 0);
/* Enable SERR */
- reg32 = pci_read_config32(mch, PCI_COMMAND);
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(mch, PCI_COMMAND, reg32);
+ pci_or_config16(mch, PCI_COMMAND, PCI_COMMAND_SERR);
}
static const char *northbridge_acpi_name(const struct device *dev)
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 83bc60eece..856eab3301 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -147,12 +147,8 @@ static void mch_domain_set_resources(struct device *dev)
static void mch_domain_init(struct device *dev)
{
- u32 reg32;
-
/* Enable SERR */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
}
static const char *northbridge_acpi_name(const struct device *dev)
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 45b6ce3248..9c32dae275 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -131,12 +131,8 @@ static void mch_domain_set_resources(struct device *dev)
static void mch_domain_init(struct device *dev)
{
- u32 reg32;
-
/* Enable SERR */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
}
static const char *northbridge_acpi_name(const struct device *dev)