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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-29 16:26:14 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-06 09:39:46 +0100
commit6220eec18816f816cae28c07c6afcaf1673d83c6 (patch)
treed67374dfc6b6ad59ba03573244f319deb28cb587 /src/northbridge/intel
parent810e2cde30035d0de691805041ffeeff57f68027 (diff)
downloadcoreboot-6220eec18816f816cae28c07c6afcaf1673d83c6.tar.xz
intel/fsp_rangeley: Switch to MMCONF_SUPPORT_DEFAULT
Boards with this chipset do not have any reference of MMCONF_BASE_ADDRESS being written to chipset registers. Either board support is already broken or FSP takes care of this early and Kconfig lacks the notice that this parameter must match with the chosen FSP binary. CPU bootblock associated with this chipset uses exclusive PCI IO access already. Untested. Change-Id: I07d20d81266ff6aaa6384d20a806d52fd4568e08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17547 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/fsp_rangeley/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/Kconfig b/src/northbridge/intel/fsp_rangeley/Kconfig
index 6a9dbe944c..506a913729 100644
--- a/src/northbridge/intel/fsp_rangeley/Kconfig
+++ b/src/northbridge/intel/fsp_rangeley/Kconfig
@@ -17,7 +17,7 @@
config NORTHBRIDGE_INTEL_FSP_RANGELEY
bool
select CPU_INTEL_FSP_MODEL_406DX
- select MMCONF_SUPPORT
+ select MMCONF_SUPPORT_DEFAULT
if NORTHBRIDGE_INTEL_FSP_RANGELEY