diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-03 12:16:24 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-05 07:53:48 +0000 |
| commit | 6fcd7b8eb1ee650daa939593e8cbb3939f7c1188 (patch) | |
| tree | 0abd85cd08ef06b2d089711a2a3463a454d8ea7f /src/northbridge/intel | |
| parent | c2ccc9782d1151efb7eba3ea92feded2ed555391 (diff) | |
| download | coreboot-6fcd7b8eb1ee650daa939593e8cbb3939f7c1188.tar.xz | |
cpu/intel/model_206ax: Switch to POSTCAR_STAGE
Tested on Lenovo Thinkpad X220 with both native raminit and mrc.bin.
Change-Id: I5e1a1175d79af4dc079a5a08a464eef08de0bcbf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sandybridge/Kconfig | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/ram_calc.c | 14 |
3 files changed, 13 insertions, 7 deletions
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index fce1a49092..f727453afe 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -21,6 +21,8 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI select RELOCATABLE_RAMSTAGE + select POSTCAR_STAGE + select POSTCAR_CONSOLE config NORTHBRIDGE_INTEL_IVYBRIDGE bool @@ -29,6 +31,8 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI select RELOCATABLE_RAMSTAGE + select POSTCAR_STAGE + select POSTCAR_CONSOLE if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index d08b141b3d..3d8da0c4bc 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -46,4 +46,6 @@ romstage-y += ../../../arch/x86/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +postcar-y += ram_calc.c + endif diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index cf583c030c..6199a6272d 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -46,9 +46,10 @@ void *cbmem_top(void) #define ROMSTAGE_RAM_STACK_SIZE 0x5000 -/* setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -void *setup_stack_and_mtrrs(void) +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -76,8 +77,7 @@ void *setup_stack_and_mtrrs(void) * handler as well as using the TSEG region for other purposes. */ postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + + /* We do not return here. */ } |