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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-26 18:33:31 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-03-28 18:02:02 +0000 |
| commit | 7ee1c47cbaccadbba72a9207ad9089792b0e6964 (patch) | |
| tree | 34acd8bb0083b715ed3c7057bec9978d1a5ee2d1 /src/northbridge/intel | |
| parent | 738331885680b99fadafba92f1cf3e2a76fd8624 (diff) | |
| download | coreboot-7ee1c47cbaccadbba72a9207ad9089792b0e6964.tar.xz | |
nb/intel/pineview: Correct HICLKGTCTL write
Reference code uses the `0x06` as an or-mask, which makes more sense.
Change-Id: I04e5262d9ab36ae866fccd90255e4a0f85328e85
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51859
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/pineview/raminit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 965adaef2f..680f3c901b 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -2320,7 +2320,7 @@ static void sdram_powersettings(struct sysinfo *s) MCHBAR8_AND(CISDCTRL + 3, ~0x80); MCHBAR16_AND(CICGDIS, ~0x1fff); MCHBAR32_AND(SBCLKGATECTRL, ~0x0001ffff); - MCHBAR16_AND(HICLKGTCTL, ~0x03ff & 0x06); + MCHBAR16_AND_OR(HICLKGTCTL, ~0x03ff, 0x06); MCHBAR32_AND_OR(HTCLKGTCTL, ~0xffffffff, 0x20); MCHBAR8_AND(TSMISC, ~1); MCHBAR8(C0WRDPYN) = s->selected_timings.CAS - 1 + 0x15; |