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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-22 22:53:19 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-11 08:56:55 +0100
commit811932a61411f5258096e734a158be01c00cf940 (patch)
tree70c12a7b16900133f9a9aaa43b6705da3f9c0aa0 /src/northbridge/intel
parent9d8adc0e3a923e1d201d50344f94a9176e5ec939 (diff)
downloadcoreboot-811932a61411f5258096e734a158be01c00cf940.tar.xz
intel i945 gm45 x4x: Apply cbmem_top() alignment
Force modest 4 MiB alignment to help with MTRR assignment. Change-Id: I49a7d1288bc079da1b8bd52150ddcfcfe2e51179 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17780 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/gm45/ram_calc.c7
-rw-r--r--src/northbridge/intel/i945/ram_calc.c7
-rw-r--r--src/northbridge/intel/x4x/ram_calc.c9
3 files changed, 19 insertions, 4 deletions
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 146bcf2c7f..c22b491c66 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -82,9 +82,14 @@ static uintptr_t smm_region_start(void)
return tor;
}
+/* Depending of UMA and TSEG configuration, TSEG might start at any
+ * 1 MiB aligment. As this may cause very greedy MTRR setup, push
+ * CBMEM top downwards to 4 MiB boundary.
+ */
void *cbmem_top(void)
{
- return (void *) smm_region_start();
+ uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB);
+ return (void *) top_of_ram;
}
void *setup_stack_and_mtrrs(void)
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 39ede5f75b..d962cc3daa 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -54,9 +54,14 @@ static uintptr_t smm_region_start(void)
return tom;
}
+/* Depending of UMA and TSEG configuration, TSEG might start at any
+ * 1 MiB aligment. As this may cause very greedy MTRR setup, push
+ * CBMEM top downwards to 4 MiB boundary.
+ */
void *cbmem_top(void)
{
- return (void *) smm_region_start();
+ uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB);
+ return (void *) top_of_ram;
}
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 09eec47e72..2a5d7e5752 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -89,10 +89,15 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
return 1;
}
+/* Depending of UMA and TSEG configuration, TSEG might start at any
+ * 1 MiB aligment. As this may cause very greedy MTRR setup, push
+ * CBMEM top downwards to 4 MiB boundary.
+ */
void *cbmem_top(void)
{
- u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG);
- return (void*)(ramtop);
+ uintptr_t top_of_ram = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG);
+ top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB);
+ return (void *) top_of_ram;
}
void *setup_stack_and_mtrrs(void)