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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-25 11:40:00 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-11 08:58:07 +0100
commit8183025be9febdc8169db376d200537806772208 (patch)
treed53eaff8a76b4213db7d9cd4ca823d4262703029 /src/northbridge/intel
parenta6ac1877316216c8c56a9ab04b9ac3cde6ab01aa (diff)
downloadcoreboot-8183025be9febdc8169db376d200537806772208.tar.xz
intel/i945: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Scratchpad register was read too late in ramstage so acpi_is_wakeup_s3() did not evaluate correctly. This fixes low memory corruption at 0x1000-0x102c and the lack of coreboot tables (util/cbmem not working) after S3 resume. This also fixes console log from reporting early in ramstage "Normal boot" while on "S3 resume" path. Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17675 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/i945/early_init.c12
-rw-r--r--src/northbridge/intel/i945/northbridge.c23
2 files changed, 2 insertions, 33 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 8ebb422551..377302a235 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -21,6 +21,7 @@
#include <device/pci_def.h>
#include <cbmem.h>
#include <halt.h>
+#include <romstage_handoff.h>
#include <string.h>
#include "i945.h"
#include <pc80/mc146818rtc.h>
@@ -197,7 +198,6 @@ static void i945_setup_bars(void)
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC);
printk(BIOS_DEBUG, " done.\n");
/* Wait for MCH BAR to come up */
@@ -901,15 +901,7 @@ static void i945_prepare_resume(int s3resume)
cbmem_was_initted = !cbmem_recovery(s3resume);
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume && cbmem_was_initted) {
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
- SKPAD_ACPI_S3_MAGIC);
- }
+ romstage_handoff_init(cbmem_was_initted && s3resume);
}
void i945_late_initialization(int s3resume)
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 6226a6382a..5092b1799b 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -175,26 +175,6 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
-#if CONFIG_HAVE_ACPI_RESUME
-static void northbridge_init(struct device *dev)
-{
- switch (pci_read_config32(dev, SKPAD)) {
- case SKPAD_NORMAL_BOOT_MAGIC:
- printk(BIOS_DEBUG, "Normal boot.\n");
- acpi_slp_type = 0;
- break;
- case SKPAD_ACPI_S3_MAGIC:
- printk(BIOS_DEBUG, "S3 Resume.\n");
- acpi_slp_type = 3;
- break;
- default:
- printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
- acpi_slp_type = 0;
- break;
- }
-}
-#endif
-
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
};
@@ -204,9 +184,6 @@ static struct device_operations mc_ops = {
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.acpi_fill_ssdt_generator = generate_cpu_entries,
-#if CONFIG_HAVE_ACPI_RESUME
- .init = northbridge_init,
-#endif
.scan_bus = 0,
.ops_pci = &intel_pci_ops,
};