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authorArthur Heymans <arthur@aheymans.xyz>2016-10-27 23:56:08 +0200
committerMartin Roth <martinroth@google.com>2016-11-08 22:48:48 +0100
commit8a3514d0aebd0839ab848d45618db3b4a253e1ab (patch)
treeb04dffb7d7d1aaf9f5ac01da38278640bbd1f11b /src/northbridge/intel
parent1d04d16b08dcb8e38aeebe7ed8e7f966049dd313 (diff)
downloadcoreboot-8a3514d0aebd0839ab848d45618db3b4a253e1ab.tar.xz
nb/x4x/raminit.c: Improve crossclock table cosmetics
Change-Id: I3f692c55fdff99aa9eb41eaaea79a41ac93be590 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17170 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/x4x/raminit_ddr2.c87
1 files changed, 55 insertions, 32 deletions
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index cd5b3b2817..fbd6191710 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -175,39 +175,62 @@ static void clkcross_ddr2(struct sysinfo *s)
u8 i, j;
MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15);
-#define TAB_M667F800 {0x1f1f1f1f, 0x1a07070b, 0x0, 0x10000000, 0x20010208, \
- 0x04080000, 0x10010002, 0x0, 0x0, 0x02000000, \
- 0x04000100, 0x08000000, 0x10200204}
-#define TAB_M800F800 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x08010204, \
- 0x0, 0x08010204, 0x0, 0x0, 0x0, 0x00020001, 0x0, 0x04080102}
-#define TAB_M667F1067 {0x6d5b1f1f, 0x0f0f0f0f, 0x0, 0x20000000, 0x80020410, \
- 0x02040008, 0x10000100, 0x0, 0x0, 0x04000000, \
- 0x08000102, 0x20000000, 0x40010208}
-#define TAB_M800F1067 {0x07070707, 0x06030303, 0x0, 0x0, 0x08010200, \
- 0x0, 0x04000102, 0x0, 0x0, 0x0, 0x00020001, \
- 0x0, 0x02040801}
-#define TAB_M1067F1067 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x04080102, \
- 0x0, 0x08010204, 0x0, 0x0, 0x0, 0x00020001, \
- 0x0, 0x02040801}
-#define TAB_M667F1333 {0x05050303, 0xffffffff, 0xffff0000, 0x0, 0x08020000, \
- 0x0, 0x00020001, 0x0, 0x0, 0x0, 0x08010204, \
- 0x0, 0x04010000}
-#define TAB_M800F1333 {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x0, 0x10020400, \
- 0x02000000, 0x00040100, 0x0, 0x0, 0x04080000, \
- 0x00100102, 0x0, 0x08100200}
-#define TAB_M1067F1333 {0x0f0f0f0f, 0x5b1f1f6d, 0x0, 0x0, 0x08010204, \
- 0x04000000, 0x00080102, 0x0, 0x0, 0x02000408, \
- 0x00100001, 0x0, 0x04080102}
-#define TAB_M1333F1333 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x04080102, \
- 0x0, 0x04080102, 0x0, 0x0, 0x0, 0x0, 0x0, 0x02040801}
-
static const u32 clkxtab[6][3][13] = {
- {{}, {}, {}}, // MEMCLK 400 N/A
- {{}, {}, {}}, // MEMCLK 533 N/A
- {TAB_M667F800, TAB_M667F1067, TAB_M667F1333, },
- {TAB_M800F800, TAB_M800F1067, TAB_M800F1333, },
- {{}, TAB_M1067F1067, TAB_M1067F1333, },
- {{}, {}, TAB_M1333F1333, },
+ /* MEMCLK 400 N/A */
+ {{}, {}, {} },
+ /* MEMCLK 533 N/A */
+ {{}, {}, {} },
+ /* MEMCLK 667
+ * FSB 800 */
+ {{0x1f1f1f1f, 0x1a07070b, 0x00000000, 0x10000000,
+ 0x20010208, 0x04080000, 0x10010002, 0x00000000,
+ 0x00000000, 0x02000000, 0x04000100, 0x08000000,
+ 0x10200204},
+ /* FSB 1067 */
+ {0x6d5b1f1f, 0x0f0f0f0f, 0x00000000, 0x20000000,
+ 0x80020410, 0x02040008, 0x10000100, 0x00000000,
+ 0x00000000, 0x04000000, 0x08000102, 0x20000000,
+ 0x40010208},
+ /* FSB 1333 */
+ {0x05050303, 0xffffffff, 0xffff0000, 0x00000000,
+ 0x08020000, 0x00000000, 0x00020001, 0x00000000,
+ 0x00000000, 0x00000000, 0x08010204, 0x00000000,
+ 0x04010000} },
+ /* MEMCLK 800
+ * FSB 800 */
+ {{0xffffffff, 0x05030305, 0x0000ffff, 0x0000000,
+ 0x08010204, 0x00000000, 0x08010204, 0x0000000,
+ 0x00000000, 0x00000000, 0x00020001, 0x0000000,
+ 0x04080102},
+ /* FSB 1067 */
+ {0x07070707, 0x06030303, 0x00000000, 0x00000000,
+ 0x08010200, 0x00000000, 0x04000102, 0x00000000,
+ 0x00000000, 0x00000000, 0x00020001, 0x00000000,
+ 0x02040801},
+ /* FSB 1333 */
+ {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x00000000,
+ 0x10020400, 0x02000000, 0x00040100, 0x00000000,
+ 0x00000000, 0x04080000, 0x00100102, 0x00000000,
+ 0x08100200} },
+ /* MEMCLK 1067 */
+ {{},
+ /* FSB 1067 */
+ {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000,
+ 0x04080102, 0x00000000, 0x08010204, 0x00000000,
+ 0x00000000, 0x00000000, 0x00020001, 0x00000000,
+ 0x02040801},
+ /* FSB 1333 */
+ {0x0f0f0f0f, 0x5b1f1f6d, 0x00000000, 0x00000000,
+ 0x08010204, 0x04000000, 0x00080102, 0x00000000,
+ 0x00000000, 0x02000408, 0x00100001, 0x00000000,
+ 0x04080102} },
+ /* MEMCLK 1333 */
+ {{}, {},
+ /* FSB 1333 */
+ {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000,
+ 0x04080102, 0x00000000, 0x04080102, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x02040801} }
};
i = (u8)s->selected_timings.mem_clk;