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authorArthur Heymans <arthur@aheymans.xyz>2019-01-15 20:14:33 +0100
committerArthur Heymans <arthur@aheymans.xyz>2019-05-25 15:49:27 +0000
commit99e578e3c1697028957f25efc7c14d1cb4d405dc (patch)
tree44853df46744994d5caf3172a579f9d92252155b /src/northbridge/intel
parentc752c500fbcc055e8cdfb30a2e523e8a9349b79f (diff)
downloadcoreboot-99e578e3c1697028957f25efc7c14d1cb4d405dc.tar.xz
nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c. Tested on Foxconn D41S. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/pineview/Kconfig1
-rw-r--r--src/northbridge/intel/pineview/Makefile.inc2
-rw-r--r--src/northbridge/intel/pineview/bootblock.c6
-rw-r--r--src/northbridge/intel/pineview/pineview.h1
-rw-r--r--src/northbridge/intel/pineview/romstage.c8
5 files changed, 7 insertions, 11 deletions
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index 1878cc4f38..2b4f502c61 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -33,6 +33,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select SMM_TSEG
select PARALLEL_MP
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
+ select C_ENVIRONMENT_BOOTBLOCK
config BOOTBLOCK_NORTHBRIDGE_INIT
string
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
index 90a9f48373..c72fe3ee57 100644
--- a/src/northbridge/intel/pineview/Makefile.inc
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -16,6 +16,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y)
+bootblock-y += bootblock.c
+
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c
index bd76fb933c..bd510b00ee 100644
--- a/src/northbridge/intel/pineview/bootblock.c
+++ b/src/northbridge/intel/pineview/bootblock.c
@@ -12,11 +12,13 @@
*/
#include <device/pci_ops.h>
-#define PCIEXBAR 0x60
+#include <cpu/intel/car/bootblock.h>
+#include "pineview.h"
+
#define MMCONF_256_BUSSES 16
#define ENABLE 1
-static void bootblock_northbridge_init(void)
+void bootblock_early_northbridge_init(void)
{
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR,
CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE);
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index 65d21cfb8d..f53ff17aa3 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -236,7 +236,6 @@ u32 decode_igd_gtt_size(const u32 gsm);
u8 decode_pciebar(u32 *const base, u32 *const len);
/* Mainboard romstage callback functions */
-void mb_enable_lpc(void);
void get_mb_spd_addrmap(u8 *spd_addr_map);
void mb_pirq_setup(void); /* optional */
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index 41fb0f6720..8d7de45149 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -57,20 +57,12 @@ void mainboard_romstage_entry(unsigned long bist)
if (bist == 0)
enable_lapic();
- /* Disable watchdog timer */
- RCBA32(GCS) = RCBA32(GCS) | 0x20;
-
/* Enable GPIOs */
pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
- mb_enable_lpc(); // nm10_enable_lpc
-
- /* Initialize console device(s) */
- console_init();
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);