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authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-04-13 16:56:23 +0200
committerPatrick Rudolph <siro@das-labor.org>2019-04-16 08:58:41 +0000
commitad0b48222ffd894f1b8f78e7de8a6ee139fc17c9 (patch)
tree66d38257c482200385a4f2347af116c020434c66 /src/northbridge/intel
parent41dad286d846819242a84fc65faed2bbb35845ac (diff)
downloadcoreboot-ad0b48222ffd894f1b8f78e7de8a6ee139fc17c9.tar.xz
sb/intel/i82801ix: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Use common code to detect ACPI S3. Untested. Change-Id: I618d4c25adb0d2b9bbd59a3b3b84beac78db1916 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/gm45/romstage.c15
1 files changed, 2 insertions, 13 deletions
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index 09439f25ef..15d3c3a344 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -27,6 +27,7 @@
#include <northbridge/intel/gm45/gm45.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmclib.h>
#include <string.h>
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
@@ -82,19 +83,7 @@ void mainboard_romstage_entry(unsigned long bist)
DMIBAR16(0x204) &= ~(3 << 10);
/* Check for S3 resume. */
- const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
- if (((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- s3resume = 1;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
+ s3resume = southbridge_detect_s3_resume();
/* RAM initialization */
enter_raminit_or_reset();