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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-09 20:24:20 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-10 22:33:12 +0200 |
| commit | c9848a82e23f826adb97a251031b0625e9809b24 (patch) | |
| tree | a09023329c19e7ae131a4a43ce04888e39968b5d /src/northbridge/intel | |
| parent | 519c4b7298516c849b4a510ad2fd691d662de7d6 (diff) | |
| download | coreboot-c9848a82e23f826adb97a251031b0625e9809b24.tar.xz | |
intel/i945: Use "IS_ENABLED" for fsbclk & memclk
Change-Id: I3213a8664955239b10bcf1784ce1ba5e0d95688b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16958
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 41 |
1 files changed, 18 insertions, 23 deletions
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 0b9e95c011..5248b00d38 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -106,10 +106,8 @@ void sdram_dump_mchbar_registers(void) static int memclk(void) { - int offset = 0; -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM - offset++; -#endif + int offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; + switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { case 1: return 400; case 2: return 533; @@ -119,29 +117,26 @@ static int memclk(void) return -1; } -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM static u16 fsbclk(void) { - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 400; - case 1: return 533; - case 3: return 667; - default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); - } - return 0xffff; -} -#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC -static u16 fsbclk(void) -{ - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 1066; - case 1: return 533; - case 2: return 800; - default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + switch (MCHBAR32(CLKCFG) & 7) { + case 0: return 400; + case 1: return 533; + case 3: return 667; + default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); + } + return 0xffff; + } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + switch (MCHBAR32(CLKCFG) & 7) { + case 0: return 1066; + case 1: return 533; + case 2: return 800; + default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); + } + return 0xffff; } - return 0xffff; } -#endif static int sdram_capabilities_max_supported_memory_frequency(void) { |