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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-02 08:56:05 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-07 13:00:56 +0100
commite25b5ef39fd10e48e87e0c4770a721a786e36a36 (patch)
tree113c2b4eba9bf7fddd6badbafc3c0f6ac0cef04f /src/northbridge/intel
parent3d15e10aef5811e8c7146e5defb0e36b848547ed (diff)
downloadcoreboot-e25b5ef39fd10e48e87e0c4770a721a786e36a36.tar.xz
MMCONF_SUPPORT: Consolidate resource registration
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/fsp_rangeley/northbridge.c27
-rw-r--r--src/northbridge/intel/fsp_sandybridge/northbridge.c46
-rw-r--r--src/northbridge/intel/i3100/northbridge.c10
-rw-r--r--src/northbridge/intel/i945/northbridge.c45
-rw-r--r--src/northbridge/intel/nehalem/Kconfig4
-rw-r--r--src/northbridge/intel/nehalem/northbridge.c11
-rw-r--r--src/northbridge/intel/sandybridge/northbridge.c46
7 files changed, 52 insertions, 137 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c
index f01333e4a0..0134eff568 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.c
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.c
@@ -57,13 +57,12 @@ int bridge_silicon_revision(void)
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 384;
-static int get_pcie_bar(u32 *base, u32 *len)
+static int get_pcie_bar(u32 *base)
{
device_t dev;
u32 pciexbar_reg;
*base = 0;
- *len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev)
@@ -76,25 +75,13 @@ static int get_pcie_bar(u32 *base, u32 *len)
*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28));
- *len = 256 * 1024 * 1024; /* 256MB ECAM range */
- return 1;
+ return 256;
}
static int add_fixed_resources(struct device *dev, int index)
{
struct resource *resource;
- u32 pcie_config_base, pcie_config_size;
-
- if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
- printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
- "size=0x%x\n", pcie_config_base, pcie_config_size);
- resource = new_resource(dev, index++);
- resource->base = (resource_t) pcie_config_base;
- resource->size = (resource_t) pcie_config_size;
- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
- }
resource = new_resource(dev, index++); /* Local APIC */
resource->base = LAPIC_DEFAULT_BASE;
@@ -154,9 +141,19 @@ static void mc_add_dram_resources(device_t dev)
static void mc_read_resources(device_t dev)
{
+ u32 pcie_config_base;
+ int buses;
+
/* Call the normal read_resources */
pci_dev_read_resources(dev);
+ /* We use 0xcf as an unused index for our PCIe bar so that we find it again */
+ buses = get_pcie_bar(&pcie_config_base);
+ if (buses) {
+ struct resource *resource = new_resource(dev, 0xcf);
+ mmconf_resource_init(resource, pcie_config_base, buses);
+ }
+
/* Calculate and add DRAM resources. */
mc_add_dram_resources(dev);
}
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c
index 50615b5f2d..c9f6e1c061 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.c
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c
@@ -62,13 +62,12 @@ int bridge_silicon_revision(void)
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 384;
-static int get_pcie_bar(u32 *base, u32 *len)
+static int get_pcie_bar(u32 *base)
{
device_t dev;
u32 pciexbar_reg;
*base = 0;
- *len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev)
@@ -82,16 +81,13 @@ static int get_pcie_bar(u32 *base, u32 *len)
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
- *len = 256 * 1024 * 1024;
- return 1;
+ return 256;
case 1: // 128M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
- *len = 128 * 1024 * 1024;
- return 1;
+ return 128;
case 2: // 64M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
- *len = 64 * 1024 * 1024;
- return 1;
+ return 64;
}
return 0;
@@ -99,21 +95,8 @@ static int get_pcie_bar(u32 *base, u32 *len)
static void add_fixed_resources(struct device *dev, int index)
{
- struct resource *resource;
- u32 pcie_config_base, pcie_config_size;
-
mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
- if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
- printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
- "size=0x%x\n", pcie_config_base, pcie_config_size);
- resource = new_resource(dev, index++);
- resource->base = (resource_t) pcie_config_base;
- resource->size = (resource_t) pcie_config_size;
- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
- }
-
mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);
}
@@ -256,24 +239,17 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev)
{
- struct resource *resource;
+ u32 pcie_config_base;
+ int buses;
pci_dev_read_resources(dev);
- /* So, this is one of the big mysteries in the coreboot resource
- * allocator. This resource should make sure that the address space
- * of the PCIe memory mapped config space bar. But it does not.
- */
-
/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
- resource = new_resource(dev, 0xcf);
- resource->base = DEFAULT_PCIEXBAR;
- resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
- resource->flags =
- IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
- IORESOURCE_ASSIGNED;
- printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
- (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
+ buses = get_pcie_bar(&pcie_config_base);
+ if (buses) {
+ struct resource *resource = new_resource(dev, 0xcf);
+ mmconf_resource_init(resource, pcie_config_base, buses);
+ }
}
static void mc_set_resources(device_t dev)
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index 8025ac3cbb..4549f85f4f 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -32,9 +32,6 @@
#include <arch/acpi.h>
-static u32 max_bus;
-
-
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
@@ -139,14 +136,9 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev)
{
- struct resource *resource;
-
pci_dev_read_resources(dev);
- resource = new_resource(dev, 0xcf);
- resource->base = 0xe0000000;
- resource->size = max_bus * 4096*256;
- resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+ mmconf_resource(dev, 0xcf);
}
static void mc_set_resources(device_t dev)
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 5d1859133c..c027bece88 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -27,13 +27,12 @@
#include <arch/acpi.h>
#include "i945.h"
-static int get_pcie_bar(u32 *base, u32 *len)
+static int get_pcie_bar(u32 *base)
{
device_t dev;
u32 pciexbar_reg;
*base = 0;
- *len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev)
@@ -47,36 +46,18 @@ static int get_pcie_bar(u32 *base, u32 *len)
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
- *len = 256 * 1024 * 1024;
- return 1;
+ return 256;
case 1: // 128M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
- *len = 128 * 1024 * 1024;
- return 1;
+ return 128;
case 2: // 64M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
- *len = 64 * 1024 * 1024;
- return 1;
+ return 64;
}
return 0;
}
-static void add_fixed_resources(struct device *dev, int index)
-{
- struct resource *resource;
- u32 pcie_config_base, pcie_config_size;
-
- if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
- printk(BIOS_DEBUG, "Adding PCIe config bar\n");
- resource = new_resource(dev, index++);
- resource->base = (resource_t) pcie_config_base;
- resource->size = (resource_t) pcie_config_size;
- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
- }
-}
-
static void pci_domain_set_resources(device_t dev)
{
uint32_t pci_tolm;
@@ -153,8 +134,6 @@ static void pci_domain_set_resources(device_t dev)
uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10);
mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10);
- add_fixed_resources(dev, 7);
-
assign_resources(dev->link_list);
}
@@ -173,19 +152,17 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev)
{
- struct resource *resource;
+ u32 pcie_config_base;
+ int buses;
pci_dev_read_resources(dev);
/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
- resource = new_resource(dev, 0xcf);
- resource->base = DEFAULT_PCIEXBAR;
- resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
- resource->flags =
- IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
- IORESOURCE_ASSIGNED;
- printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
- (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
+ buses = get_pcie_bar(&pcie_config_base);
+ if (buses) {
+ struct resource *resource = new_resource(dev, 0xcf);
+ mmconf_resource_init(resource, pcie_config_base, buses);
+ }
}
static void mc_set_resources(device_t dev)
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index 4dada50aaf..884660ad88 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -24,6 +24,10 @@ config NORTHBRIDGE_INTEL_NEHALEM
if NORTHBRIDGE_INTEL_NEHALEM
+config MMCONF_BUS_NUMBER
+ int
+ default 256
+
config CBFS_SIZE
hex
default 0x100000
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 06c0a9655b..779e49cd54 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -69,11 +69,6 @@ static void add_fixed_resources(struct device *dev, int index)
0xfed1c000-0xfed20000 RCBA
0xfed90000-0xfed94000 IOMMU
0xff800000-0xffffffff ROM. */
- resource = new_resource(dev, index++);
- resource->base = (resource_t) 0xe0000000;
- resource->size = (resource_t) 0x10000000;
- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
resource = new_resource(dev, index++);
resource->base = (resource_t) 0xfed00000;
@@ -98,10 +93,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
}
- /* TODO We could determine how many PCIe busses we need in
- * the bar. For now that number is hardcoded to a max of 64.
- * See e7525/northbridge.c for an example.
- */
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
@@ -119,6 +110,8 @@ static void mc_read_resources(device_t dev)
pci_dev_read_resources(dev);
+ mmconf_resource(dev, 0x50);
+
tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)),
D0F0_TOUUD);
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index fe1a07c570..7f7c842324 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -61,13 +61,12 @@ int bridge_silicon_revision(void)
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 384;
-static int get_pcie_bar(u32 *base, u32 *len)
+static int get_pcie_bar(u32 *base)
{
device_t dev;
u32 pciexbar_reg;
*base = 0;
- *len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev)
@@ -81,16 +80,13 @@ static int get_pcie_bar(u32 *base, u32 *len)
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
- *len = 256 * 1024 * 1024;
- return 1;
+ return 256;
case 1: // 128M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
- *len = 128 * 1024 * 1024;
- return 1;
+ return 128;
case 2: // 64M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
- *len = 64 * 1024 * 1024;
- return 1;
+ return 64;
}
return 0;
@@ -98,21 +94,8 @@ static int get_pcie_bar(u32 *base, u32 *len)
static void add_fixed_resources(struct device *dev, int index)
{
- struct resource *resource;
- u32 pcie_config_base, pcie_config_size;
-
mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
- if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
- printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
- "size=0x%x\n", pcie_config_base, pcie_config_size);
- resource = new_resource(dev, index++);
- resource->base = (resource_t) pcie_config_base;
- resource->size = (resource_t) pcie_config_size;
- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
- }
-
mmio_resource(dev, index++, legacy_hole_base_k,
(0xc0000 >> 10) - legacy_hole_base_k);
reserved_ram_resource(dev, index++, 0xc0000 >> 10,
@@ -276,24 +259,17 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev)
{
- struct resource *resource;
+ u32 pcie_config_base;
+ int buses;
pci_dev_read_resources(dev);
- /* So, this is one of the big mysteries in the coreboot resource
- * allocator. This resource should make sure that the address space
- * of the PCIe memory mapped config space bar. But it does not.
- */
-
/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
- resource = new_resource(dev, 0xcf);
- resource->base = DEFAULT_PCIEXBAR;
- resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
- resource->flags =
- IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
- IORESOURCE_ASSIGNED;
- printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
- (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
+ buses = get_pcie_bar(&pcie_config_base);
+ if (buses) {
+ struct resource *resource = new_resource(dev, 0xcf);
+ mmconf_resource_init(resource, pcie_config_base, buses);
+ }
}
static void mc_set_resources(device_t dev)