Various 440BX and Tyan S1846 related minor changes and fixes (trivial):

 - Only check the RAM from 0 - 640 KB and 768 KB - 1 MB now. That's
   available on all boards, regardless of what DIMMs you use.
   Tested on the Tyan S1846, works fine.

 - Properly set the PAM registers to allow the region from 768 KB - 1 MB
   to be used as normal RAM (required for the above).

 - Document all of this properly. Add/improve other documentation, too.

 - Simplify and document code in northbridge.c.

 - Cosmetics and coding style.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 44 insertions, 32 deletions

diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index 59f09193ce..f28ba1bd14 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -92,44 +92,41 @@ static uint32_t find_pci_tolm(struct bus *bus)
 static void pci_domain_set_resources(device_t dev)
 {
 	device_t mc_dev;
-        uint32_t pci_tolm;
+	uint32_t pci_tolm;
 
-        pci_tolm = find_pci_tolm(&dev->link[0]);
+	pci_tolm = find_pci_tolm(&dev->link[0]);
 	mc_dev = dev->link[0].children;
 
 	if (mc_dev) {
-		/* Figure out which areas are/should be occupied by RAM.
-		 * This is all computed in kilobytes and converted to/from
-		 * the memory controller right at the edges.
-		 * Having different variables in different units is
-		 * too confusing to get right.  Kilobytes are good up to
-		 * 4 Terabytes of RAM...
-		 */
 		uint16_t tolm_r;
 		unsigned long tomk, tolmk;
 		int idx;
 
-		/* Get the value of the highest DRB. This tells the end of
-		 * the physical memory.  The units are ticks of 8MB
-		 * i.e. 1 means 8MB.
+		/* Figure out which areas are/should be occupied by RAM. The
+		 * value of the highest DRB denotes the end of the physical
+		 * memory (in units of 8MB).
 		 */
-		tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7)) << 13; 
-		printk_debug("Setting RAM size to %d MB\n", tomk >> 10);
+		tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7));
+
+		/* Convert to KB. */
+		tomk *= (8 * 1024);
+
+		printk_debug("Setting RAM size to %d MB\n", tomk / 1024);
+
+		/* Compute the top of low memory. */
+		tolmk = pci_tolm / 1024;
 
-		/* Compute the top of Low memory */
-		tolmk = pci_tolm >> 10;
 		if (tolmk >= tomk) {
-			/* The PCI hole does does not overlap the memory.
-			 */
+			/* The PCI hole does does not overlap the memory. */
 			tolmk = tomk;
 		}
 
-		/* Report the memory regions */
+		/* Report the memory regions. */
 		idx = 10;
 		ram_resource(dev, idx++, 0, 640);
-		// ram_resource(dev, idx++, 768, tolmk - 768);
-		ram_resource(dev, idx++, 1024, tolmk - 1024);
+		ram_resource(dev, idx++, 768, tolmk - 768);
 	}
+
 	assign_resources(&dev->link[0]);
 }
 
@@ -179,6 +176,6 @@ static void enable_dev(struct device *dev)
 }
 
 struct chip_operations northbridge_intel_i440bx_ops = {
-	CHIP_NAME("Intel 440BX Northbridge")
+	CHIP_NAME("Intel 82443BX (440BX) Northbridge")
 	.enable_dev = enable_dev,
 };
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 08219741f0..b51a0e67b4 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -69,7 +69,7 @@ static const uint32_t refresh_rate_map[] = {
 /* Table format: register, bitmask, value. */
 static const long register_values[] = {
 	/* NBXCFG - NBX Configuration Register
-	 * 0x50
+	 * 0x50 - 0x53
 	 *
 	 * [31:24] SDRAM Row Without ECC
 	 *         0 = ECC components are populated in this row
@@ -158,6 +158,7 @@ static const long register_values[] = {
 
 	/*
 	 * PAM[6:0] - Programmable Attribute Map Registers
+	 * 0x59 - 0x5f
 	 *
 	 * 0x59 [3:0] Reserved
 	 * 0x59 [5:4] 0xF0000 - 0xFFFFF BIOS area
@@ -181,13 +182,13 @@ static const long register_values[] = {
 	 * 11 = Read/Write (all access goes to DRAM)
 	 */
 	// TODO
-	PAM0, 0x00000000, 0x00,
-	PAM1, 0x00000000, 0x00,
-	PAM2, 0x00000000, 0x00,
-	PAM3, 0x00000000, 0x00,
-	PAM4, 0x00000000, 0x00,
-	PAM5, 0x00000000, 0x00,
-	PAM6, 0x00000000, 0x00,
+	PAM0, 0x00, 0x00,
+	PAM1, 0x00, 0x00,
+	PAM2, 0x00, 0x00,
+	PAM3, 0x00, 0x00,
+	PAM4, 0x00, 0x00,
+	PAM5, 0x00, 0x00,
+	PAM6, 0x00, 0x00,
 
 	/* DRB[0:7] - DRAM Row Boundary Registers
 	 * 0x60 - 0x67
@@ -204,7 +205,7 @@ static const long register_values[] = {
 	 * 0x66 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB)
 	 * 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB)
 	 */
-	// TODO
+	/* Set the DRBs to zero for now, this will be fixed later. */
 	DRB0, 0x00, 0x00,
 	DRB1, 0x00, 0x00,
 	DRB2, 0x00, 0x00,
@@ -424,7 +425,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 
 	max = sizeof(register_values) / sizeof(register_values[0]);
 
-	/* Set registers as specified in the register_values array. */
+	/* Set registers as specified in the register_values[] array. */
 	for (i = 0; i < max; i += 3) {
 		reg = pci_read_config32(ctrl->d0, register_values[i]);
 		reg &= register_values[i + 1];
@@ -448,7 +449,21 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 {
 	/* TODO: Don't hardcode the values here, get info via SPD. */
 
+	/* Map all legacy regions to RAM (read/write). This is required if
+	 * you want to use the RAM area from 768 KB - 1 MB. If the PAM
+	 * registers are not set here appropriately, the RAM in that region
+	 * will not be accessible, thus a RAM check of it will also fail.
+	 */
+	pci_write_config8(ctrl->d0, PAM0, 0x30);
+	pci_write_config8(ctrl->d0, PAM1, 0x33);
+	pci_write_config8(ctrl->d0, PAM2, 0x33);
+	pci_write_config8(ctrl->d0, PAM3, 0x33);
+	pci_write_config8(ctrl->d0, PAM4, 0x33);
+	pci_write_config8(ctrl->d0, PAM5, 0x33);
+	pci_write_config8(ctrl->d0, PAM6, 0x33);
+
 	/* TODO: Set DRB0-DRB7. */
+	/* Currently this is hardcoded to one 64 MB DIMM in slot 0. */
 	pci_write_config8(ctrl->d0, DRB0, 0x08);
 	pci_write_config8(ctrl->d0, DRB1, 0x08);
 	pci_write_config8(ctrl->d0, DRB2, 0x08);