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authorDamien Zammit <damien@zamaudio.com>2016-01-22 19:11:05 +1100
committerMartin Roth <martinroth@google.com>2016-01-29 00:18:58 +0100
commitfe9876a7631c7982fccf38692dbed955e229f47b (patch)
tree7937ae57aa91c923976a711eae96416d316c64a3 /src/northbridge/intel
parent9fb08f55a86467ba1a36d4f5e6196a77b534778d (diff)
downloadcoreboot-fe9876a7631c7982fccf38692dbed955e229f47b.tar.xz
nb/intel/x4x: Tidy up northbridge
- Add device enable macros - Set the PMBASE correctly through southbridge device Change-Id: I1b8cc3de96b1ecaf01e31bad8fba1fada8671c2d Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/x4x/early_init.c11
-rw-r--r--src/northbridge/intel/x4x/x4x.h11
2 files changed, 13 insertions, 9 deletions
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index b98c42eb5d..b52229367f 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -22,8 +22,6 @@
void x4x_early_init(void)
{
- u16 reg16;
-
const device_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */
@@ -36,12 +34,11 @@ void x4x_early_init(void)
pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
/* Setup PMBASE */
- pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80);
/* Setup HECIBAR */
pci_write_config32(PCI_DEV(0,3,0), 0x10, DEFAULT_HECIBAR);
- reg16 = pci_read_config16(PCI_DEV(0,3,0), 0x4);
- pci_write_config16(PCI_DEV(0,3,0), 0x4, reg16 | 0x6);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(d0f0, D0F0_PAM(0), 0x30);
@@ -53,8 +50,6 @@ void x4x_early_init(void)
pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
/* Enable internal GFX */
+ pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
pci_write_config16(d0f0, D0F0_GGC, 0x0170);
-
- reg16 = pci_read_config16(d0f0, D0F0_DEVEN);
- pci_write_config16(d0f0, D0F0_DEVEN, reg16 | 0x8);
}
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index c2269504a1..e1ef745867 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -27,11 +27,20 @@
#define D0F0_MCHBAR_HI 0x4c
#define D0F0_GGC 0x52
#define D0F0_DEVEN 0x54
+#define D0EN (1 << 0)
+#define D1EN (1 << 1)
+#define IGD0EN (1 << 3)
+#define IGD1EN (1 << 4)
+#define D3F0EN (1 << 6)
+#define D3F1EN (1 << 7)
+#define D3F2EN (1 << 8)
+#define D3F3EN (1 << 9)
+#define PEG1EN (1 << 13)
+#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN)
#define D0F0_PCIEXBAR_LO 0x60
#define D0F0_PCIEXBAR_HI 0x64
#define D0F0_DMIBAR_LO 0x68
#define D0F0_DMIBAR_HI 0x6c
-#define D0F0_PMBASE 0x78
#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/
#define D0F0_REMAPBASE 0x98
#define D0F0_REMAPLIMIT 0x9a