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| author | Nico Huber <nico.h@gmx.de> | 2017-09-09 19:46:44 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-09-10 17:49:27 +0000 |
| commit | 0b80bd1cf4510b3a4f028b5bb5570a2806c22320 (patch) | |
| tree | e7d8854664e59ee3193a6c4e30c37713a04de50b /src/northbridge/intel | |
| parent | 3b4b069a0c8bf255c81a798c138b413f02415a5c (diff) | |
| download | coreboot-0b80bd1cf4510b3a4f028b5bb5570a2806c22320.tar.xz | |
nb/intel/i945: Clear timeout bits after disabling watchdog
Even with the watchdog disabled, these bits influence other hardware
blocks (e.g. SECOND_TO_STS stops SMBus block transfers, possibly yet
before they started).
Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 1d473d3104..0abd42eec8 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -170,6 +170,8 @@ static void i945_setup_bars(void) printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + outw((1 << 3), DEFAULT_PMBASE | 0x60 | 0x04); /* clear timeout */ + outw((1 << 1), DEFAULT_PMBASE | 0x60 | 0x06); /* clear 2nd timeout */ printk(BIOS_DEBUG, " done.\n"); /* Enable upper 128bytes of CMOS */ |