diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-05 17:37:49 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-06 10:39:01 +0000 |
| commit | 45b824d69433a630147dd690f6b5993bc2d4bb76 (patch) | |
| tree | d1ceebb6eedcc9aa0818b4a1326400123b4c9042 /src/northbridge/intel | |
| parent | 0a7543db2d9938fe449d800f0b2e61ffefd7b822 (diff) | |
| download | coreboot-45b824d69433a630147dd690f6b5993bc2d4bb76.tar.xz | |
src: Remove unused include <halt.h>
Change-Id: I2f142cc80692e60eb0f81f57339a247f6ef4a524
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/raminit.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/romstage.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 1 |
6 files changed, 0 insertions, 6 deletions
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index fddada4ba0..96dc94e7d2 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -20,7 +20,6 @@ #include <arch/cbfs.h> #include <cbfs.h> #include <cf9_reset.h> -#include <halt.h> #include <ip_checksum.h> #include <memory_info.h> #include <mrc_cache.h> diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index a9de844f15..274296d482 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <cbmem.h> -#include <halt.h> #include <romstage_handoff.h> #include "i945.h" #include <pc80/mc146818rtc.h> diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 1e8cf65581..0cf03ae605 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -26,7 +26,6 @@ #include <pc80/mc146818rtc.h> #include <spd.h> #include <string.h> -#include <halt.h> #include "raminit.h" #include "i945.h" #include "chip.h" diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index bdb685b252..a3e6c39172 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <cbmem.h> #include <cf9_reset.h> -#include <halt.h> #include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index cea3f2cd70..e60c37875b 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -25,7 +25,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <cbmem.h> -#include <halt.h> #include <timestamp.h> #include <mrc_cache.h> #include <southbridge/intel/bd82x6x/me.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a68ae49c7c..ea3590f78d 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -28,7 +28,6 @@ #include <device/pci_def.h> #include <lib.h> #include <mrc_cache.h> -#include <halt.h> #include <timestamp.h> #include "raminit.h" #include "pei_data.h" |