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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-17 23:55:18 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-20 09:37:47 +0000 |
| commit | 78b43c8990a7e3331dd5a0bd2484a53956f546aa (patch) | |
| tree | 05c940ea7fd9c51a52689261bed5aab3605e7ee2 /src/northbridge/intel | |
| parent | 3d5d6e8dc7f95d9bcf55ad0c67bd9b6d458c43dd (diff) | |
| download | coreboot-78b43c8990a7e3331dd5a0bd2484a53956f546aa.tar.xz | |
nb/intel/sandybridge: Always write to PEGCTL
This register needs to be written to once to lock it down. Do so.
Change-Id: I04bd496d064940b51cb9aa1ded6f5b8853ea7334
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39624
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 23c1489acb..abfc1259de 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -377,11 +377,12 @@ static void disable_peg(void) /* * Set the PEG clock gating bit. Disables the IO clock on all PEG devices. * - * FIXME: If not clock gating, this register still needs to be written to once, - * to lock it down. Also, never clock gate on Ivy Bridge stepping A0! + * FIXME: Never clock gate on Ivy Bridge stepping A0! */ MCHBAR32_OR(PEGCTL, 1); printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); + } else { + MCHBAR32_AND(PEGCTL, ~1); } } |