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| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-15 02:26:29 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-09-17 20:00:17 +0000 |
| commit | b8b117c7e72ceb641c14db499a2c004fdfaf64f9 (patch) | |
| tree | 18bc8e7140eafaf1f91dee91fad9d145aec337ed /src/northbridge/intel | |
| parent | 6549661b9cc94add8c203a26f5f29af255668e4e (diff) | |
| download | coreboot-b8b117c7e72ceb641c14db499a2c004fdfaf64f9.tar.xz | |
nb/intel/x4x: Clean up TPM-related code
Perform the read to the TPM base address using <arch/mmio.h> functions.
Remove dead variable assignment and rename TPM base address macro.
Tested with BUILD_TIMELESS=1. Asus P5QL PRO remains identical.
Change-Id: I11d737903c57fce768b760fe717564dae8879ad0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/x4x/bootblock.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/iomap.h | 3 |
2 files changed, 5 insertions, 6 deletions
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 328464a440..baa4ae336c 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -1,17 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/bootblock.h> +#include <arch/mmio.h> #include <device/pci_ops.h> + #include "x4x.h" #include "iomap.h" void bootblock_early_northbridge_init(void) { - uint32_t reg32; - /* Disable LaGrande Technology (LT) */ - reg32 = TPM32(0); + read32((void *)TPM_BASE_ADDRESS); - reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1; + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1; pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32); } diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h index d016cf74af..22a675fc42 100644 --- a/src/northbridge/intel/x4x/iomap.h +++ b/src/northbridge/intel/x4x/iomap.h @@ -8,7 +8,6 @@ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_HECIBAR 0xfed10000 -#define TPMBASE 0xfed40000 -#define TPM32(x) (*((volatile u32 *)(TPMBASE + (x)))) +#define TPM_BASE_ADDRESS 0xfed40000 #endif /* X4X_IOMAP_H */ |