diff options
| author | Ryan Salsamendi <rsalsamendi@hotmail.com> | 2017-07-04 13:35:06 -0700 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-07-06 20:20:12 +0000 |
| commit | b9bc2571bebf05f9a295e80a66226064ef41b020 (patch) | |
| tree | 1b600da94f5dd2cfb1aeed3f92816f929a62314d /src/northbridge/intel | |
| parent | 70c27de57122558a0579ba7fb6517d55ed5bafc1 (diff) | |
| download | coreboot-b9bc2571bebf05f9a295e80a66226064ef41b020.tar.xz | |
northbridge/intel/haswell: Fix undefined behavior
Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: Id1ed2252ce3ed052730dd10b24c453c34c2ab4ff
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/acpi.c | 10 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/early_init.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/finalize.c | 6 |
3 files changed, 11 insertions, 7 deletions
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 8afef00baa..e032948e52 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -29,6 +29,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar = 0; u32 pciexbar_reg; int max_buses; + u32 mask; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) @@ -40,17 +41,20 @@ unsigned long acpi_fill_mcfg(unsigned long current) if (!(pciexbar_reg & (1 << 0))) return current; + mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + pciexbar = pciexbar_reg & mask; max_buses = 256; break; case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + mask |= (1 << 27); + pciexbar = pciexbar_reg & mask; max_buses = 128; break; case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + mask |= (1 << 27) | (1 << 26); + pciexbar = pciexbar_reg & mask; max_buses = 64; break; default: // RSVD diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index f4263394ad..a2b0f7fb88 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -81,7 +81,7 @@ static void haswell_setup_graphics(void) /* GPU RC6 workaround for sighting 366252 */ reg32 = MCHBAR32(0x5d14); - reg32 |= (1 << 31); + reg32 |= (1UL << 31); MCHBAR32(0x5d14) = reg32; /* VLW */ diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 5a82449fde..04f73566db 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -35,11 +35,11 @@ void intel_northbridge_haswell_finalize_smm(void) pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0); /* TOLUD */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ - MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ + MCHBAR32_OR(0x5f00, 1UL << 31); /* SA PM */ MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(0x6800, 1 << 31); - MCHBAR32_OR(0x7000, 1 << 31); + MCHBAR32_OR(0x6800, 1UL << 31); + MCHBAR32_OR(0x7000, 1UL << 31); MCHBAR32_OR(0x77fc, 1 << 0); /* Memory Controller Lockdown */ |