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| author | David Hendricks <dhendrix@chromium.org> | 2014-05-20 15:52:08 -0700 |
|---|---|---|
| committer | David Hendricks <dhendrix@chromium.org> | 2014-05-21 01:21:30 +0200 |
| commit | 03b00e9675d08d01ff831f20e8e48d19e93494af (patch) | |
| tree | 5a36345196cf65275706a729c879e4d63c533f34 /src/northbridge/intel | |
| parent | 61113de9234f1b933a084c90097ec125fc12f55d (diff) | |
| download | coreboot-03b00e9675d08d01ff831f20e8e48d19e93494af.tar.xz | |
baytrail: Fix some minor errors in FSP
- Duplicate declaration of GetFspReservedMemoryFromGuid
- Corrupt line that was only compiled for a southbridge that no
board in coreboot currently uses.
(thanks for Mike Hibbett <mhibbett@ircona.com> for pointing this out)
Change-Id: I847e807272acbaa93c87a89c0d2f94829c9121e6
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/5798
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index f7bb023b59..0537c54769 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -89,7 +89,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) /* Initialize the UPD Data */ - GetUpdDefaultFromFsp (fsp_ptr, fsp_upd_data);/home/martin/extra/git/coreboot + GetUpdDefaultFromFsp (fsp_ptr, fsp_upd_data); ConfigureDefaultUpdData(fsp_upd_data); #else pFspRtBuffer->Platform.MemoryConfig = &MemoryConfig; |