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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-09-22 12:22:24 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-05-01 17:42:30 +0000 |
| commit | 16a70a48c68f9027b0900e15fc9e3bc14391ad44 (patch) | |
| tree | 70409c259f50e463913d068a00d1e0f600f8a578 /src/northbridge/intel | |
| parent | dfce932cf0c3d13f41892d6e40d56fbaa8e16240 (diff) | |
| download | coreboot-16a70a48c68f9027b0900e15fc9e3bc14391ad44.tar.xz | |
nb/intel/x4x: Change memory layout to improve MTRR
This change also makes sure that the sum the uma regions (TSEG, GSM,
GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between
2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR
setup for ramstage. At least tianocore requires this and fails to boot
without it.
Better MTRR are achieved by making the memory 'hole' till 4GiB exactly
2Gib.
This code mimics how it is done in nb/intel/gm45 and achieves similar
results.
TSEG is enabled and set to 8M since this makes it easier to reuse the
common smm setup / parallel mp code and makes it possible to cache the
ramstage in there like how it's done on newer targets.
TESTED on Intel DG43GT.
Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/x4x/early_init.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/raminit_ddr2.c | 13 |
2 files changed, 16 insertions, 3 deletions
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index ab4864b880..d410259d82 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -74,7 +74,11 @@ void x4x_early_init(void) get_option(&gfxsize, "gfx_uma_size"); if (gfxsize > 12) gfxsize = 6; - pci_write_config16(d0f0, D0F0_GGC, 0x0100 | (gfxsize + 1) << 4); + /* Need at least 4M for cbmem_top alignment */ + else if (gfxsize < 1) + gfxsize = 1; + /* Set GTT size to 2+2M */ + pci_write_config16(d0f0, D0F0_GGC, 0x0b00 | (gfxsize + 1) << 4); } else { /* Does not feature internal graphics */ pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN); pci_write_config16(d0f0, D0F0_GGC, (1 << 1)); diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 04dad085de..ddbcd5b700 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -1293,18 +1293,22 @@ static void mmap_ddr2(struct sysinfo *s) bool reclaim; u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud; u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; + u32 mmiostart, umasizem; u16 ggc; u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; + u8 reg8; ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; - tsegsize = 1; // 1MB TSEG + tsegsize = 8; // 8MB TSEG mmiosize = 0x800; // 2GB MMIO + umasizem = gfxsize + gttsize + tsegsize; + mmiostart = 0x1000 - mmiosize + umasizem; tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; - tolud = MIN(0x1000 - mmiosize, tom); + tolud = MIN(mmiostart, tom); reclaim = false; if ((tom - tolud) > 0x40) @@ -1336,6 +1340,11 @@ static void mmap_ddr2(struct sysinfo *s) pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud); pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20); pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20); + /* Enable and set tseg size to 8M */ + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); + reg8 &= ~0x7; + reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */ + pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8); pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20); } |