diff options
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-02-12 12:00:44 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-04-04 13:44:47 +0000 |
| commit | 2f828ebb59fe680ccc6d75793d8c411996130883 (patch) | |
| tree | f6e141efb17dc34f6c555e32847e59abbb9be9f7 /src/northbridge/intel | |
| parent | 0b861daeccaeeebec7d82ac534e0c102e4733aa7 (diff) | |
| download | coreboot-2f828ebb59fe680ccc6d75793d8c411996130883.tar.xz | |
nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbers
This is hopefully more readable.
TEST=Build lenovo/x200 with and without this patch (using make
BUILD_TIMELESS=1), compare build/coreboot.rom, notice no differences.
Change-Id: I079d5353633a3d58ce0e5e616f3fad687a064d65
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23709
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index af5faf0caf..08f954d057 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1804,10 +1804,12 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Perform receive-enable calibration. */ raminit_receive_enable_calibration(timings, dimms); /* Lend clock values from receive-enable calibration. */ - MCHBAR32(0x1224) = (MCHBAR32(0x1224) & ~(0xf0)) | - ((((MCHBAR32(0x121c) >> 7) - 1) & 0xf) << 4); - MCHBAR32(0x1324) = (MCHBAR32(0x1324) & ~(0xf0)) | - ((((MCHBAR32(0x131c) >> 7) - 1) & 0xf) << 4); + MCHBAR32(CxDRT5_MCHBAR(0)) = + (MCHBAR32(CxDRT5_MCHBAR(0)) & ~(0xf0)) | + ((((MCHBAR32(CxDRT3_MCHBAR(0)) >> 7) - 1) & 0xf) << 4); + MCHBAR32(CxDRT5_MCHBAR(1)) = + (MCHBAR32(CxDRT5_MCHBAR(1)) & ~(0xf0)) | + ((((MCHBAR32(CxDRT3_MCHBAR(1)) >> 7) - 1) & 0xf) << 4); /* Perform read/write training for high clock rate. */ if (timings->mem_clock == MEM_CLOCK_1067MT) { |